[论文解读] A Comparison of High-Level Design Tools for SoC-FPGA on Disparity Map Calculation Example

Shaodong Qin, Mladen Bereković|arXiv (Cornell University)|Aug 28, 2015

CCD and CMOS Imaging Sensors参考文献 10被引用 4

一句话总结

本文评估了Vivado HLS和Altera SDK for OpenCL在SoC-FPGA上用于稠密匹配图计算加速的高层次设计工具。结果表明，两种工具均能显著缩短开发时间，实现快速硬件加速器开发；其中Vivado HLS提供更精细的控制，但需要更高的硬件专业知识；而OpenCL更易于使用，但为实现相当的性能会消耗更多FPGA资源。

ABSTRACT

Modern SoC-FPGA that consists of FPGA with embedded ARM cores is being popularized as an embedded vision system platform. However, the design approach of SoC-FPGA applications still follows traditional hardware-software separate workflow, which becomes the barrier of rapid product design and iteration on SoC-FPGA. High-Level Synthesis (HLS) and OpenCL-based system-level design approaches provide programmers the possibility to design SoC-FGPA at system-level with an unified development environment for both hardware and software. To evaluate the feasibility of high-level design approach especially for embedded vision applications, Vivado HLS and Altera SDK for OpenCL, representative and most popular commercial tools in market, are selected as evaluation design tools, disparity map calculation as targeting application. In this paper, hardware accelerators of disparity map calculation are designed with both tools and implemented on Zedboard and SoCKit development board, respectively. Comparisons between design tools are made in aspects of supporting directives, accelerator design process, and generated hardware performance. The results show that both tools can generate efficient hardware for disparity map calculation application with much less developing time. Moreover, we can also state that, more directives (e.g., interface type, array reshape, resource type specification) are supported, but more hardware knowledge is required, in Vivado HLS. In contrast, Altera SDK for OpenCL is relatively easier for software programmers who is new to hardware, but with the price of more resources usage on FPGA for similar hardware accelerator generation.

研究动机与目标

• 评估高层次综合与基于OpenCL的设计在SoC-FPGA上用于嵌入式视觉应用的可行性。
• 从开发效率、硬件性能和资源利用率角度，比较Vivado HLS与Altera SDK for OpenCL。
• 评估高层次设计工具中硬件控制与程序员易用性之间的权衡。
• 为SoC-FPGA开发工作流中的设计工具选择提供实用见解。

提出的方法

• 在Zedboard上使用Vivado HLS实现稠密匹配图计算加速器。
• 在SoCKit开发板上使用Altera SDK for OpenCL实现相同应用。
• 基于支持的指令、开发流程复杂度以及生成的硬件性能，评估两种工具。
• 测量两种加速器的性能与资源使用情况（LUTs、BRAMs、DSPs）。
• 采用标准的稠密匹配图计算算法作为目标应用，以确保比较的一致性。
• 在开发时间、资源消耗和性能指标方面进行对比。

实验结果

研究问题

• RQ1 在SoC-FPGA设计中，Vivado HLS与Altera SDK for OpenCL在开发时间和易用性方面有何差异？
• RQ2 由Vivado HLS与OpenCL生成的加速器在稠密匹配图计算中的性能差异如何？
• RQ3 两种工具在支持硬件优化指令（如接口类型、数组重排）方面有何不同？
• RQ4 与HLS相比，OpenCL在实现相似性能时的资源利用率开销如何？
• RQ5 先前的硬件知识在多大程度上影响了每种工具的有效性？

主要发现

• Vivado HLS与Altera SDK for OpenCL均显著缩短了与传统软硬件协同设计工作流相比的开发时间。
• Vivado HLS支持更多低级指令（如接口类型、数组重排、资源类型），但需要更深入的硬件知识。
• Altera SDK for OpenCL对初次接触硬件的软件开发者更友好，但为实现同等性能会消耗更多FPGA资源。
• 两种工具生成的加速器在稠密匹配图计算中均表现出高效性能，验证了高层次设计在嵌入式视觉应用中的可行性。
• 由于对硬件生成具有更精确的控制，Vivado HLS在资源效率方面表现更优。
• 基于OpenCL的设计通过抽象硬件复杂性提升了生产力，但以更高的资源消耗为代价，表明存在生产力与效率之间的权衡。