[论文解读] A New Gate for Optimal Fault Tolerant & Testable Reversible Sequential Circuit Design.

Vishal Pareek|arXiv (Cornell University)|Oct 9, 2014

Quantum Computing Algorithms and Architecture参考文献 23被引用 3

一句话总结

本硕士论文提出一种新型的保 parity 可逆门——Pareek 门，并设计了优化的、容错的且可测试的可逆时序电路，包括 D、R-S、J-K 和 T 触发器、移位寄存器及计数器。与现有可逆电路相比，所提出的电路在门数、垃圾输出、常量输入和量子成本方面均取得显著改进，且在固定故障和单比特故障的在线与离线可测试性方面有新贡献。

ABSTRACT

With phenomenal growth of high speed and complex computing applications, the design of low power and high speed logic circuits have created tremendous interest. Conventional computing devices are based on irreversible logic and further reduction in power consumption and/or increase in speed appears non-promising. Reversible computing has emerged as a solution looking to the power and speed requirements of future computing devices. In reversible computing logic gates used are such that input can be generated by reversing the operation from output. A number of reversible combinational circuits have been developed but the growth of sequential circuits was not significant due to feedback and fanout was not allowed. However, allowing feedback in space, a very few sequential logic blocks i.e. flip-flops have been reported in literature. In order to develop sequential circuits, flip-flops are used in conventional circuits. Also good circuit design methods, optimized and fault tolerant designs are also needed to build large, complex and reliable circuits in conventional computing. Reversible flip-flops are the basic memory elements that will be the building block of memory for reversible computing and quantum computing devices. In this dissertation we plan to address above issues. First we have proposed a Pareek gate suitable for low-cost flip-flops design and then design methodology to develop flip-flops are illustrated. Further almost all flip-flops and some example circuit have been developed and finally these circuits have been converted into fault tolerant circuits by preserving their parity and designs of offline as well as online testable circuits have been proposed. In this dissertation work, we have also compared quantum cost as well as other parameters with existing circuits and shown a significant improvement in almost all parameters.

研究动机与目标

• . 设计一种新型保 parity 的可逆门，以改进时序电路的构建。
• . 开发门数更少、硬件复杂度和量子成本更低的优化可逆触发器（D、R-S、J-K、T）
• . 实现能够检测单比特故障和固定故障的容错可逆时序元件。
• . 为可逆 D 触发器引入新颖的离线与在线可测试性机制。
• . 设计资源开销最小的高效可逆移位寄存器与计数器。

提出的方法

• . 提出 Pareek 门作为一种新型可逆逻辑门，具备保 parity 特性。
• . 使用 Toffoli 和 CNOT 门实现 Pareek 门，并给出其量子电路实现。
• . 利用所提出的门设计正逻辑与负逻辑的 D、R-S、J-K 和 T 触发器，以最小化门数与垃圾输出。
• . 实现主从式与双边沿触发的 D 触发器，以增强容错能力。
• . 提出基于奇偶校验的故障检测机制，实现 D 触发器的离线与在线可测试性方案。
• . 设计资源使用优化的可逆 SIPO、PISO 移位寄存器及移位寄存器计数器。

实验结果

研究问题

• RQ1 . 如何设计一种新型可逆门，以在时序电路中保持 parity 并减少资源开销？
• RQ2 . 如何实现可逆 D、R-S、J-K 和 T 触发器的最优实现，以最小化量子成本与垃圾输出？
• RQ3 . 如何有效将容错机制集成到可逆时序电路中，以检测单比特故障与固定故障？
• RQ4 . 可逆 D 触发器最有效的离线与在线可测试性策略是什么？
• RQ5 . 如何在可逆逻辑中优化移位寄存器与计数器，以实现最小的资源消耗？

主要发现

• . 所提出的 Pareek 门相比现有可逆门，可减少门数与量子成本。
• . 可逆 D 触发器设计相比先前工作，门数与垃圾输出减少 30-40%。
• . 容错 D 触发器设计可检测固定故障与单比特故障，且面积开销极小。
• . 首次在可逆逻辑中提出在线可测试 D 触发器设计，实现故障的实时检测。
• . 可逆移位寄存器与计数器设计在量子成本与硬件复杂度方面均有显著改进。
• . 所提设计成本效益高，适用于基于新兴纳米技术的未来可逆计算系统。