[论文解读] An Asynchronous Early Output Full Adder and a Relative-Timed Ripple Carry Adder

P. Balasubramanian|arXiv (Cornell University)|May 12, 2016

Low-power high-performance VLSI design参考文献 42被引用 10

一句话总结

本文提出了一种异步早期输出全加器，实现了具有数据相关前向延迟和恒定1周期反向延迟的相对定时进位先行加法器（RCA），与优化后的强指示异步RCA相比，前向延迟降低67%，周期时间减少83%，面积减少27%，且在32/28nm CMOS工艺中保持相近的功耗损耗。

ABSTRACT

This article presents the design of a new asynchronous early output full adder which when cascaded leads to a relative-timed ripple carry adder (RCA). The relative-timed RCA requires imposing a very small relative-timing assumption to overcome the problem of gate orphans associated with internal carry propagation. The relative-timing assumption is however independent of the RCA size. The primary benefits of the relative-timed RCA are processing of valid data incurs data-dependent forward latency, while the processing of spacer involves a very fast constant time reverse latency of just 1 full adder delay which represents the ultimate in the design of an asynchronous RCA with the fastest reset. The secondary benefits of the relative-timed RCA are it achieves good optimization of power and area metrics simultaneously. A 32-bit relative-timed RCA constructed using the proposed early output full adder achieves respective reductions in forward latency by 67%, 10% and 3.5% compared to the optimized strong-indication, weak-indication, and early output 32-bit asynchronous RCAs existing in the literature. Based on a similar comparison, the proposed 32-bit relative-timed RCA achieves corresponding reductions in cycle time by 83%, 12.7% and 6.4%. In terms of area, the proposed 32-bit relative-timed RCA occupies 27% less Silicon than its optimized strong-indication counterpart and 17% less Silicon than its optimized weak-indication counterpart, and features increased area occupancy by a meager 1% compared to the optimized early output 32-bit asynchronous RCA. The average power dissipation of all the asynchronous 32-bit RCAs are found to be comparable since they all satisfy the monotonic cover constraint. The simulation results obtained correspond to a 32/28nm CMOS process.

研究动机与目标

• 解决由于内部进位传播导致的异步进位先行加法器中的门孤岛问题。
• 在保持快速复位能力的同时，降低异步RCA的前向延迟。
• 同时优化异步加法器设计中的面积和功耗效率。
• 实现一种可扩展的、基于相对定时的RCA，其定时假设与加法器大小无关。

提出的方法

• 设计一种异步早期输出全加器，基于输入跳变尽可能早地生成有效的和与进位输出。
• 将早期输出全加器级联，构建一种具有最小相对定时假设的相对定时进位先行加法器。
• 施加一个微小且与尺寸无关的相对定时约束，以防止内部进位传播期间出现门孤岛。
• 采用单调覆盖约束，确保功耗效率，并在所有异步设计中保持相近的功耗损耗。
• 通过恰好一个全加器延迟的反向延迟实现RCA，以实现异步RCA设计中最快可能的复位。
• 针对32/28nm CMOS工艺进行电路优化，并通过仿真评估面积和性能指标。

实验结果

研究问题

• RQ1 如何设计异步进位先行加法器，以在避免门孤岛的同时最小化前向延迟？
• RQ2 相对定时方法是否能实现异步RCA中更快的复位和更低的面积消耗？
• RQ3 早期输出全加器在异步加法器中能在多大程度上降低周期时间和前向延迟？
• RQ4 与现有的强指示、弱指示及早期输出异步RCA相比，所提设计在面积和功耗方面表现如何？
• RQ5 相对定时假设是否随RCA大小而扩展，还是与位数无关？

主要发现

• 32位相对定时RCA相比优化后的强指示异步RCA，前向延迟降低了67%。
• 与强指示对应设计相比，所提RCA的周期时间减少了83%。
• 该设计的硅面积比优化后的强指示RCA减少27%，比弱指示版本减少17%。
• 与优化后的早期输出RCA相比，面积仅增加1%，表明具有很高的面积效率。
• 由于遵循单调覆盖约束，所有设计的平均功耗损耗保持相近。
• 反向延迟固定为一个全加器延迟，代表了异步RCA设计中最快可能的复位。