[论文解读] An Energy-efficient Time-domain Analog VLSI Neural Network Processor Based on a Pulse-width Modulation Approach

Masatoshi Yamaguchi, Goki Iwamoto+2 more|arXiv (Cornell University)|Feb 16, 2019

Advanced Memory and Neural Computing参考文献 25被引用 7

一句话总结

该论文提出一种基于脉宽调制（PWM）的时域模拟VLSI神经网络处理器，用于二值神经网络中能量高效的加权和计算。通过利用亚阈值MOSFET及瞬态RC充放电机制，该设计在250-nm CMOS工艺下实现了300 TOPS/W的能效，较当前最先进的数字AI处理器高出30倍以上，若采用先进工艺，潜在能效可达1,000 TOPS/W以上。

ABSTRACT

A time-domain analog-weighted-sum calculation model based on a pulse-width modulation (PWM) approach is proposed. The proposed calculation model can be applied to any types of network structure including multi-layer feedforward networks. We also propose very large-scale integrated (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits used in computing-in-memory circuits, our time-domain analog circuits use transient operation in charging/discharging processes to capacitors. Since the circuits can be designed without operational amplifiers, they can be operated with extremely low power consumption. However, they have to use very high-resistance devices, on the order of giga-ohms. We designed a CMOS VLSI chip to verify weighted-sum operation based on the proposed model with binary weights, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors unlike the ordinary computing-in-memory circuits. The chip was designed and fabricated using a 250-nm fabrication technology. Measurement results showed that energy efficiency for the weighted-sum calculation was 300~TOPS/W (Tera-Operations Per Second per Watt), which is more than one order of magnitude higher than that in state-of-the-art digital AI processors, even though the minimum width of interconnection used in this chip was several times larger than that in such digital processors. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000~TOPS/W will be possible. For practical applications, development of emerging analog memory devices such as ferroelectric-gate field effect transistors (FeFETs) is necessary.

研究动机与目标

• 通过开发面向神经网络推理的低功耗模拟VLSI解决方案，解决边缘设备中数字AI处理器功耗过高的问题。
• 通过引入基于瞬态RC响应的时域模拟计算方法，克服传统模拟电压/电流模式电路的局限性。
• 利用PWM编码信号与亚阈值MOSFET，实现在二值神经网络中加权和（MAC）运算的超高速能效。
• 展示采用100×10突触的CMOS VLSI芯片，实现300 TOPS/W的能效，验证TACT-PWM方法的可行性。
• 识别出需要采用新兴模拟存储器件（如FeFET）以提升精度并补偿亚阈值工作下的器件失配问题。

提出的方法

• 提出一种基于脉宽调制（PWM）的时域模拟加权和模型，其中输入脉冲宽度表示信号幅度，电容充电过程实现加权输入的积分。
• 采用RC电路与开关电流源（SCS）实现计算，电容上的电荷累积对应于加权和。
• 利用MOSFET的亚阈值工作状态，构建高阻值元件（吉欧姆量级），实现低功耗运行，无需运算放大器。
• 采用250-nm工艺设计CMOS VLSI芯片，使用SRAM存储单元实现二值权重，并设计比较器电路实现ReLU激活。
• 应用TACT-PWM方法实现BinaryConnect网络，通过电容的瞬态充放电实现高效MAC运算。
• 通过多次测量的平均来降低定时抖动，提升输出脉冲宽度的精度。

实验结果

研究问题

• RQ1 基于PWM与瞬态RC响应的时域模拟VLSI架构，能否在神经网络推理中显著超越数字AI处理器的能效？
• RQ2 亚阈值MOSFET工作状态如何在无需运算放大器的情况下实现模拟加权和电路的超低功耗？
• RQ3 采用250-nm工艺与二值权重实现TACT-PWM模型的CMOS VLSI芯片，其可实现的能效水平如何？
• RQ4 亚阈值MOSFET中的器件失配在多大程度上降低计算精度，又如何进行补偿？
• RQ5 采用先进VLSI工艺与新兴模拟存储器件（如FeFET）可带来多大性能提升？

主要发现

• 所制造的CMOS VLSI芯片实现了300 TOPS/W的功耗效率，较当前最先进的数字AI处理器高出30倍以上。
• 尽管采用250-nm工艺（最小特征尺寸约为现代数字AI芯片的10倍），仍实现了300 TOPS/W的能效。
• 测量结果显示，ReLU激活后输出脉冲宽度的最大误差为8%，平均误差为1.5%，表明对二值网络而言精度可接受。
• 输出脉冲宽度的定时抖动为±20 ns，考虑到最大脉冲宽度为2 μs，精度约为±1%。
• 理论估算表明，若采用最先进的VLSI工艺，能效可超过1,000 TOPS/W或达到1 POPS/W。
• 神经元电路的功耗与突触阵列相当，表明比较器电路是进一步提升能效的关键瓶颈。