[论文解读] Analysis of Quantum Approximate Optimization Algorithm under Realistic Noise in Superconducting Qubits

Mahabubul Alam, Abdullah Ash Saki+1 more|arXiv (Cornell University)|Jul 13, 2019

Quantum Computing Algorithms and Architecture参考文献 16被引用 34

一句话总结

该论文分析超导量子比特上的现实噪声如何影响 QAOA 的性能，表明最佳 QAOA 深度 p 受硬件噪声（门错误、相干时间）的约束，且提高 p 不一定带来提升。

ABSTRACT

The quantum approximate optimization algorithm (QAOA) is a promising quantum-classical hybrid technique to solve combinatorial optimization problems in near-term gate-based noisy quantum devices. In QAOA, the objective is a function of the quantum state, which itself is a function of the gate parameters of a multi-level parameterized quantum circuit (PQC). A classical optimizer varies the continuous gate parameters to generate distributions (quantum state) with significant support to the optimal solution. Even at the lowest circuit depth, QAOA offers non-trivial provable performance guarantee which is expected to increase with the circuit depth. However, the existing analysis fails to consider non-idealities in the qubit quality i.e., short lifetime and imperfect gate operations in realistic quantum hardware. In this article, we investigate the impact of various noise sources on the performance of QAOA both in simulation and on a real quantum computer from IBM. Our analyses indicate that the optimal number of stages (p-value) for any QAOA instance is limited by the noise characteristics (gate error, coherence time, etc.) of the target hardware as opposed to the current perception that higher-depth QAOA will provide monotonically better performance for a given problem compared to the low-depth implementations.

研究动机与目标

• Motivate analysis of QAOA performance on NISQ devices with realistic noise and finite coherence times.
• Quantify how different noise sources (gate errors, relaxation, dephasing) limit QAOA performance with increasing depth.
• Demonstrate both simulation and experimental results on IBMQX4 for MaxCut using QAOA.
• Establish bounds on the optimal p-value based on hardware characteristics and problem size.

提出的方法

• Model a 6-qubit fully connected quantum computer with IBMQX4-like noise characteristics (T1=45 μs, T2=20 μs, gate errors for CNOT and single-qubit gates).
• Implement MaxCut-QAOA with cost Hamiltonian H_C and mixing Hamiltonian H_B using hardware-native gates (CNOT, RX, RZ).
• Simulate QAOA under depolarizing, amplitude damping, and phase damping channels for gate errors, relaxation, and dephasing via operator-sum formalism.
• Run experiments on IBMQX4 and compare with noiseless simulations to assess impact of noise on parameter landscapes and solution quality.
• Employ a global optimizer (differential evolution) to find optimal (γ,β) for each instance across p=1–4.

实验结果

研究问题

• RQ1 How do realistic noise sources (gate errors, relaxation, dephasing) affect QAOA performance as depth p increases?
• RQ2 What is the bound on the optimal QAOA depth p given specific hardware characteristics (cost Hamiltonian time vs coherence times)?
• RQ3 How do different problem graphs (MaxCut on small graphs) behave under noisy QAOA compared to ideal simulations?
• RQ4 Can the cost Hamiltonian fidelity and execution time explain degradation or improvement of QAOA with depth under realistic noise?

主要发现

• Optimal QAOA depth p is bounded by hardware noise and coherence times; higher p does not guarantee better performance in realistic devices.
• For given graphs, relaxation (T1) and dephasing (T2) times constrain p, with p improving up to a point when circuit time remains favorable relative to coherence times.
• Gate errors, especially two-qubit gate errors, can significantly degrade QAOA performance at higher p, reducing or negating gains from deeper circuits.
• Cost Hamiltonian fidelity decays with circuit depth and gate errors, leading to substantial changes in the solution space and reduced probability of best solutions.
• Simulations and IBMQX4 experiments show that optimal p shifts with hardware parameters; larger graphs and longer executions exacerbate noise-induced limitations.