[论文解读] Assessment of error variation in high-fidelity two-qubit gates in silicon

Tuomo Tanttu, Wee Han Lim+25 more|arXiv (Cornell University)|Mar 7, 2023

Semiconductor materials and devices参考文献 49被引用 9

一句话总结

该论文在 SiMOS 量子点中使用 IRB、GST 和快速贝叶斯层析，量化高保真度两量子比特门的一致性，在多个设备和扩展运行中实现门保真度从 96.8% 到 99.8%。

ABSTRACT

Achieving high-fidelity entangling operations between qubits consistently is essential for the performance of multi-qubit systems and is a crucial factor in achieving fault-tolerant quantum processors. Solid-state platforms are particularly exposed to errors due to materials-induced variability between qubits, which leads to performance inconsistencies. Here we study the errors in a spin qubit processor, tying them to their physical origins. We leverage this knowledge to demonstrate consistent and repeatable operation with above 99% fidelity of two-qubit gates in the technologically important silicon metal-oxide-semiconductor (SiMOS) quantum dot platform. We undertake a detailed study of these operations by analysing the physical errors and fidelities in multiple devices through numerous trials and extended periods to ensure that we capture the variation and the most common error types. Physical error sources include the slow nuclear and electrical noise on single qubits and contextual noise. The identification of the noise sources can be used to maintain performance within tolerance as well as inform future device fabrication. Furthermore, we investigate the impact of qubit design, feedback systems, and robust gates on implementing scalable, high-fidelity control strategies. These results are achieved by using three different characterization methods, we measure entangling gate fidelities ranging from 96.8% to 99.8%. Our analysis tools identify the causes of qubit degradation and offer ways understand their physical mechanisms. These results highlight both the capabilities and challenges for the scaling up of silicon spin-based qubits into full-scale quantum processors.

研究动机与目标

• 评估硅 MOS 量子点量子比特在纠缠两量子比特门方面的时间稳定性和设备间的一致性。
• 识别来自器件设计与材料背景的物理错误机制及其产生原因。
• 评估不同门验证方法（IRB、GST、FBT）在表征门性能方面的有效性。
• 证实在较长时间和多台设备上的高保真操作持续性。
• 通过将控制策略与观测到的错误源联系起来，为自旋量子比特的扩展策略提供信息。

提出的方法

• 使用互位 J 闸来调节相邻量子点之间的交换，以实现基于交换的纠缠门。
• 比较两种门策略：单脉冲 CZ 和带有脉间去耦合的复合 DCZ 门。
• 用交错随机化基准测试（IRB）、门集层析（GST）和快速贝叶斯层析（FBT）来表征误差。
• 建立包含五个原始门的门集：X^{π/2}_{1}、X^{π/2}_{2}、Z^{π/2}_{1}、Z^{π/2}_{2} 和 CZ/DCZ。
• 分析过程矩阵以分离哈密顿量（相干）与随机（非相干）误差，并归因物理起源。
• 在三台设备（A、B、C）上测试，具有不同布局和同位素纯化水平，以及包括用于缓解缓慢漂移的反馈。

Figure 1 : Electrostatic quantum dots with tunable exchange. a , False color scanning electron micrograph (SEM) of a device similar to A and B. b , False color transmission electron micrograph (TEM) of a cross-section of a device similar to A and B. Shaded area shows the extension of electron wave f

实验结果

研究问题

• RQ1 在时间和设备间，SiMOS 设备的两量子比特门的保真度水平与误差特征为何？
• RQ2 不同门验证方法（IRB、GST、FBT）在估计保真度与诊断误差机制方面有何比较？
• RQ3 在这些硅自旋量子比特中，哪些物理源（去相干、斯塔克位移、串扰、1/f 噪声）主导了两量子比特和单量子比特门的误差？
• RQ4 是否能够在扩展运行时间和设备差异之间维持高保真纠缠门（≥99%）？
• RQ5 门设计与反馈如何影响自旋量子比特控制的可扩展性与鲁棒性？

主要发现

• 两量子比特门的保真度在 96.8% 到 99.8% 之间，覆盖了不同设备与验证方法。
• 平均 IRB 两量子比特保真度在 A 为 98.4%、B 为 99.37%、C 为 99.78%。
• 门误差分析区分哈密顿量误差与随机误差，在设备 B 中通过对相位漂移的回波降低了 IZ/Z I 与随机误差。
• GST 指出单量子比特门的目标保真度较高，但旁观量子比特去相干和串扰主导了整体门性能。
• FBT 显示在较长运行中的门保真度，在某些情况下，交错的 DCZ 提高了稳定性并避免了相位校正。
• 在三台设备中，MOS 硅自旋量子比特在总体上实现了两量子比特门保真度持续超过 99%，研究期内 IRB 的均值为 99.17%、标准差为 0.56%。

Figure 2 : Results of error characterisation methods. a , Measurement sequence principle used in randomised benchmarking. The gate of interest is interleaved with random Clifford gates that are composed of five primitive gates each. b , Simplified fast Bayesian tomography workflow from experiment to