[论文解读] CIPARSim: cache intersection property assisted rapid single-pass FIFO cache simulation technique

Mohammad Shihabul Haque, Jorgen Peddersen+1 more|arXiv (Cornell University)|Nov 7, 2011

Parallel Computing and Optimization Techniques参考文献 28被引用 10

一句话总结

CIPARSim 提出了一种名为 '交集特性' 的新型缓存属性，专为先进先出（FIFO）替换策略缓存设计，使无需完整搜索即可快速、单次遍历预测缓存命中，从而实现高效仿真。通过利用三项交集特性，CIPARSim 相较于最先进的仿真器，将仿真时间最多减少 5 倍（平均减少 3 倍），平均可准确预测高达 90% 的命中。

ABSTRACT

An application's cache miss rate is used in timing analysis, system performance prediction and in deciding the best cache memory for an embedded system to meet tighter constraints. Single-pass simulation allows a designer to find the number of cache misses quickly and accurately on various cache memories. Such single-pass simulation systems have previously relied heavily on cache inclusion properties, which allowed rapid simulation of cache configurations for different applications. Thus far the only inclusion properties discovered were applicable to the Least Recently Used (LRU) replacement policy based caches. However, LRU based caches are rarely implemented in real life due to their circuit complexity at larger cache associativities. Embedded processors typically use a FIFO replacement policy in their caches instead, for which there are no full inclusion properties to exploit. In this paper, for the first time, we introduce a cache property called the “Intersection Property” that helps to reduce single-pass simulation time in a manner similar to inclusion property. An intersection property defines conditions that if met, prove a particular element exists in larger caches, thus avoiding further search time. We have discussed three such intersection properties for caches using the FIFO replacement policy in this paper. A rapid single-pass FIFO cache simulator “CIPARSim” has also been proposed. CIPARSim is the first single-pass simulator dependent on the FIFO cache properties to reduce simulation time significantly. CIPARSim's simulation time was up to 5 times faster (on average 3 times faster) compared to the state of the art single-pass FIFO cache simulator for the cache configurations tested. CIPARSim produces the cache hit and miss rates of an application accurately on various cache configurations. During simulation, CIPARSim's intersection properties alone predict up to 90% (on average 65%) of the total hits, reducing simulation time immensely.

研究动机与目标

• 为解决嵌入式系统中常见的基于 FIFO 的缓存缺乏高效单次遍历仿真技术的问题。
• 识别并利用类似于包含性属性但适用于 FIFO 替换策略的缓存属性。
• 在不损害缓存命中与未命中率估计准确性的情况下，显著减少仿真时间。
• 开发一种实用且高性能的仿真器（CIPARSim），利用这些特性服务于实际嵌入式系统设计。

提出的方法

• 提出 '交集特性' —— 一种基于元素在更小的嵌套缓存中存在，从而推断其存在于更大缓存中的条件，而无需实际搜索。
• 定义三种适用于 FIFO 替换策略缓存的特定交集特性，实现命中预测的提前判断。
• 设计一种单次遍历仿真框架，仅处理一次缓存访问历史，利用交集特性跳过冗余搜索。
• 实现 CIPARSim 作为快速、准确的仿真器，在运行时应用这些特性以避免完整缓存查找。
• 利用交集特性提前预测缓存命中：最多 90% 的命中可无搜索预测，显著降低仿真开销。
• 优化仿真器以高效处理各种缓存配置，在保持正确性的同时提升性能。

实验结果

研究问题

• RQ1 能否为 FIFO 替换策略开发一种类似于包含性的缓存属性，以加速仿真？
• RQ2 如何形式化定义交集特性，以保证在 FIFO 缓存中正确预测命中？
• RQ3 交集特性在单次遍历 FIFO 缓存仿真中最多可将仿真时间减少多少？
• RQ4 能否基于这些特性构建一种实用仿真器，使其性能优于现有最先进的仿真器？

主要发现

• CIPARSim 相较于最先进的单次遍历 FIFO 缓存仿真器，仿真时间最多提升 5 倍。
• 在所测试的各类缓存配置下，CIPARSim 平均比现有仿真器快 3 倍。
• 仅靠交集特性，最坏情况下可预测高达 90% 的总缓存命中，平均有 65% 的命中可无搜索预测。
• CIPARSim 在多种缓存配置下均保持了高精度的命中与未命中率报告。
• 所提出的交集特性是首个使基于 FIFO 的缓存实现类似包含性优化的特性，填补了缓存仿真中的关键空白。