[论文解读] Compiler Phase Ordering as an Orthogonal Approach for Reducing Energy Consumption

Ricardo Nobre, Luís Reis+1 more|arXiv (Cornell University)|Jul 2, 2018

Parallel Computing and Optimization Techniques参考文献 15被引用 10

一句话总结

本文提出将编译器阶段排序作为一种独立的优化策略，以减少嵌入式系统和高性能计算（HPC）工作负载中的能耗，采用基于图的模型生成节能的优化阶段序列。在ARM和x86平台上的实验表明，即使未带来性能提升，也能实现最高24%的能耗降低，证明了性能优化的编译器标志（如-O3）并不总是生成最节能的代码。

ABSTRACT

Compiler writers typically focus primarily on the performance of the generated program binaries when selecting the passes and the order in which they are applied in the standard optimization levels, such as GCC -O3. In some domains, such as embedded systems and High-Performance Computing (HPC), it might be sometimes acceptable to slowdown computations if the energy consumed can be significantly decreased. Embedded systems often rely on a battery and besides energy also have power dissipation limitations, while HPC centers have a growing concern with electricity and cooling costs. Relying on power policies to apply frequency/voltage scaling and/or change the CPU to idle states (e.g., alternate between power levels in bursts) as the main method to reduce energy leaves potential for improvement using other orthogonal approaches. In this work we evaluate the impact of compiler pass sequences specialization (also known as compiler phase ordering) as a means to reduce the energy consumed by a set of programs/functions when comparing with the use of the standard compiler phase orders provided by, e.g., -OX flags. We use our phase selection and ordering framework to explore the design space in the context of a Clang+LLVM compiler targeting a multicore ARM processor in an ODROID board and a dual x86 desktop representative of a node in a Supercomputing center. Our experiments with a set of representative kernels show that there we can reduce energy consumption by up to 24% and that some of these improvements can only be partially explained by improvements to execution time. The experiments show cases where applications that run faster consume more energy. Additionally, we make an effort to characterize the compiler sequence exploration space in terms of their impact on performance and energy.

研究动机与目标

• 通过探索编译器阶段排序作为超越性能优化的独立优化维度，填补能效编译领域的空白。
• 研究定制化的编译器阶段序列是否能比标准优化级别（如-O3）更有效地降低能耗。
• 从对性能和能耗影响的角度，表征编译器阶段排序的设计空间。
• 开发并评估一种基于图的框架，用于生成针对特定函数和目标架构的节能优化阶段序列。
• 证明能效与性能并非完全相关，尤其是在动态电源管理环境下。

提出的方法

• 使用图模型表示可能的节能编译器阶段排序，该模型基于先前优化序列的统计数据进行训练。
• 在针对ARM（ODROID XU+E）和x86（双Xeon）平台的Clang+LLVM编译器中实现阶段选择与排序框架。
• 在12个PolyBench/C内核上，测量多种OpenMP线程配置下的执行时间、能耗和功耗。
• 将自定义阶段顺序的能耗与标准编译器标志（-O1至-O3）及基线序列进行比较。
• 采用留一法验证方法，评估阶段排序探索过程的有效性与可扩展性。
• 使用指纹识别与聚类技术减少编译器阶段序列的搜索空间，提升探索效率。

实验结果

研究问题

• RQ1 编译器阶段排序能否作为一种独立于标准优化级别（如-O3）的节能方法？
• RQ2 性能优化的编译器标志（如-O3）在多大程度上能实现能耗优化？其局限性何在？
• RQ3 当性能下降时，自定义阶段顺序对能耗的影响如何，相对于执行时间有何表现？
• RQ4 不同CPU架构（ARM与x86）及电源管理策略对阶段排序效果有何影响？
• RQ5 基于历史优化数据训练的图模型能否有效预测节能的阶段序列？

主要发现

• 与标准-O3优化级别相比，编译器阶段排序可将能耗降低高达24%，即使性能未提升。
• 部分程序在-O3下运行更快但能耗更高，表明性能与能效并非完全正相关。
• 自定义阶段顺序带来的能耗节省无法完全由执行时间改善解释，表明内存访问和电源状态切换等因素起关键作用。
• 基于图的阶段排序生成框架相比传统方法（如遗传算法）将探索速度提升了整整一个数量级。
• 该方法在多种平台上均有效，显著降低了基于ARM的嵌入式系统和基于x86的HPC工作站的能耗。
• 基于聚类的阶段顺序空间剪枝使探索时间相比遗传算法基线减少18倍，同时在前期工作中实现了43%的性能加速。