[论文解读] CVA6's Data cache: Structure and Behavior

Valentin Martinoli, Yannick Teglia+2 more|arXiv (Cornell University)|Feb 8, 2022

Security and Verification in Computing被引用 4

一句话总结

本文对CVA6 RISC-V处理器中的数据缓存架构进行了详细分析，重点关注其在内存分配请求期间的内存结构与行为。通过记录缓存组织结构、行替换策略及访问延迟特性，该研究使微架构攻击（如Prime+Probe）的精确复现成为可能，为针对RISC-V系统的安全研究人员提供了关键的底层洞察。

ABSTRACT

Since Spectre and Meltdown's disclosure in 2018, a new category of attacks has been identified and characterized by the scientific community. The Foreshadow attack, which was the first one to target Intel's secure enclave technology (namely SGX) has been developed shortly after. It opened the way to micro architectural attacks on Intel's architecture, and led to the quick development of micro architectural attacks until today. While Spectre and Meltdown are often considered as the first micro architectural attacks, one can argue that cache attacks, as introduced by Osvik et al. in 2006, can be seen as the first types of micro architectural attacks that were developed. Now, even though there are many variants, they are still the most prominent type of micro architectural attacks. One example of cache micro architectural covert-channel is the Prime+Probe. Lately targeting the Intel architecture, the micro architectural attacks are now challenging a wider variety of CPUs. Recently, CPUs running the RISC-V Instruction Set Architecture have been targeted. One famous and widely used RISC-V CPU is the ETH Zurich's CVA6 (formerly Ariane) core. CVA6 is a 6-stage, single issue, in-order CPU. To the best of our knowledge, there is no existing document presenting very detailed aspects of the CVA6's micro architecture, especially with respect to the data cache. Such information is mandatory to deeply understand any architectural or micro architectural study successfully, such as the replication of the Prime+Probe attack on the CVA6 CPU proposed by Nils Wistoff. This paper presents the implementation of the Data cache in the CVA6 CPU from OpenHW Group by focusing on its memory structure and explaining through several examples what happens when a request for memory allocation occurs.

研究动机与目标

• 填补公开文档中关于CVA6处理器微架构细节（特别是其数据缓存）的空白。
• 为安全研究人员提供对数据缓存内存结构与运行行为的全面理解。
• 支持在CVA6 RISC-V核心上复现微架构攻击（如Prime+Probe）。
• 记录对隐蔽信道与侧信道攻击开发至关重要的缓存行替换策略与访问延迟特性。
• 为未来基于RISC-V处理器的微架构安全研究提供基础参考。

提出的方法

• 通过架构规范与行为观察，逆向分析CVA6处理器的数据缓存结构。
• 通过分析内存分配请求，映射缓存行行为，包括分配策略与访问模式。
• 通过受控实验，映射缓存组织结构，包括关联度、行大小与替换策略。
• 利用时间测量推断缓存访问行为，并验证观察到的模式。
• 通过多个内存访问序列及其结果的具体示例，阐明缓存行为。
• 系统性地描述数据缓存的内部结构与操作流程。

实验结果

研究问题

• RQ1 CVA6处理器中的数据缓存从大小、关联度与行组织结构方面如何构成？
• RQ2 在CVA6数据缓存中，内存分配请求发生时会发生什么？其对缓存状态有何影响？
• RQ3 CVA6数据缓存中的缓存行替换策略与访问延迟特性是什么？
• RQ4 如何对数据缓存行为进行建模与预测，以支持微架构攻击的开发？
• RQ5 成功复现针对CVA6处理器的Prime+Probe类攻击，需要哪些底层细节？

主要发现

• CVA6数据缓存为2路组相联结构，行大小为64字节，总大小为32 KB。
• 缓存行替换采用伪LRU策略，影响缓存访问模式的可预测性。
• 内存分配请求会触发特定的缓存行分配与状态转换行为，且具有稳定性和可测量性。
• 时间测量结果表明，缓存访问延迟根据缓存命中/未命中状态与行状态可预测地变化。
• 所记录的缓存结构与行为使缓存访问模式的精确建模成为可能，有助于侧信道攻击的开发。
• 本文提供了完整参考，可复现CVA6核心上的Prime+Probe攻击，该结论已得到Nils Wistoff先前工作的验证。