[论文解读] Design of Synchronous Section-Carry Based Carry Lookahead Adders with Improved Figure of Merit

Padmanabhan Balasubramanian|arXiv (Cornell University)|Jun 17, 2016

Quantum-Dot Cellular Automata参考文献 22被引用 4

一句话总结

本文提出了一种基于半定制标准单元的优化同步分段进位链加法器（SCBCLA），在32/28nm CMOS工艺中，相较于先前的混合CCLA设计，其功耗-延迟-面积效率指标（FOM）提升了77.3%；相较于早期SCBCLA设计，FOM提升了88.3%。FOM定义为功耗、延迟与面积乘积的倒数，通过改进的进位前瞻生成器实现最大化，从而在32位二进制加法中实现更优的能量-延迟-面积效率。

ABSTRACT

The section-carry based carry lookahead adder (SCBCLA) architecture was proposed as an efficient alternative to the conventional carry lookahead adder (CCLA) architecture for the physical implementation of computer arithmetic. In previous related works, self-timed SCBCLA architectures and synchronous SCBCLA architectures were realized using standard cells and FPGAs. In this work, we deal with improved realizations of synchronous SCBCLA architectures designed in a semi-custom fashion using standard cells. The improvement is quantified in terms of a figure of merit (FOM), where the FOM is defined as the inverse product of power, delay and area. Since power, delay and area of digital designs are desirable to be minimized, the FOM is desirable to be maximized. Starting from an efficient conventional carry lookahead generator, we show how an optimized section-carry based carry lookahead generator is realized. In comparison with our recent work dealing with standard cells based implementation of SCBCLAs to perform 32-bit addition of two binary operands, we show in this work that with improved section-carry based carry lookahead generators, the resulting SCBCLAs exhibit significant improvements in FOM. Compared to the earlier optimized hybrid SCBCLA, the proposed optimized hybrid SCBCLA improves the FOM by 88.3%. Even the optimized hybrid CCLA features improvement in FOM by 77.3% over the earlier optimized hybrid CCLA. However, the proposed optimized hybrid SCBCLA is still the winner and has a better FOM than the currently optimized hybrid CCLA by 15.3%. All the CCLAs and SCBCLAs are implemented to realize 32-bit dual-operand binary addition using a 32/28nm CMOS process.

研究动机与目标

• 提升同步分段进位链加法器（SCBCLAs）的功耗-延迟-面积效率指标（FOM），以增强数字算术单元的能量-延迟-面积效率。
• 解决先前基于标准单元和FPGA实现的SCBCLA及CCLA设计在功耗、延迟与面积权衡方面的局限性。
• 通过优化的进位前瞻生成器，开发一种半定制的SCBCLA实现方案，以提升性能指标。
• 在相同工艺和设计条件下，将所提出的SCBCLA与现有混合CCLA及SCBCLA架构进行比较。
• 证明所提设计在FOM方面优于优化后的混合CCLA及早期SCBCLA实现。

提出的方法

• 采用高效的传统进位前瞻生成器作为所提SCBCLA设计的基础。
• 合成一种新型基于分段进位的进位前瞻生成器，以替代标准生成器，从而降低关键路径延迟和功耗。
• 在32/28nm CMOS工艺中，采用半定制方式使用标准单元实现设计，以确保物理实现效率。
• 将功耗-延迟-面积效率指标（FOM）计算为功耗、延迟与面积乘积的倒数，以定量评估性能提升。
• 在相同32位双操作数加法条件下，将所提架构与早期优化的混合CCLA及SCBCLA设计进行对比。
• 设计优化聚焦于同时最小化功耗、延迟与面积，以最大化FOM。

实验结果

研究问题

• RQ1 如何通过架构级与生成器级优化，提升同步SCBCLAs的功耗-延迟-面积效率指标（FOM）？
• RQ2 所提SCBCLA在FOM方面相较于现有混合CCLA与SCBCLA设计的相对性能提升是多少？
• RQ3 与先前基于FPGA或标准单元的实现相比，采用半定制标准单元实现方式在FOM提升方面达到何种程度？
• RQ4 优化后的基于分段进位的进位前瞻生成器是否能在保持面积效率的同时降低功耗与延迟？
• RQ5 在FOM与整体效率方面，所提SCBCLA相较于优化后的混合CCLA表现如何？

主要发现

• 所提出的优化混合SCBCLA相较于早期优化的混合SCBCLA，FOM提升了88.3%。
• 所提出的SCBCLA相较于早期优化的混合CCLA，FOM提升了77.3%。
• 所提出的SCBCLA在FOM方面相较于优化后的混合CCLA提升了15.3%，使其成为比较中性能最佳的设计。
• 所有设计（包括CCLAs与SCBCLAs）均采用32/28nm CMOS工艺实现，以确保性能评估的一致性。
• FOM的提升归因于优化后的基于分段进位的进位前瞻生成器在保持面积效率的同时降低了功耗与延迟。
• 结果证实，半定制标准单元实现方式相较于先前的FPGA与标准单元实现方式，可实现显著的FOM提升。