[论文解读] Dissecting the Graphcore IPU Architecture via Microbenchmarking

Zhe Jia, Blake Tillman+2 more|arXiv (Cornell University)|Dec 7, 2019

Advanced Memory and Neural Computing参考文献 15被引用 80

一句话总结

本文通过微基准测试分析 Graphcore IPU 架构，以理解其体系结构特征。它是 Citadel 研究人员在 2019 年撰写的技术报告。

ABSTRACT

This report focuses on the architecture and performance of the Intelligence Processing Unit (IPU), a novel, massively parallel platform recently introduced by Graphcore and aimed at Artificial Intelligence/Machine Learning (AI/ML) workloads. We dissect the IPU's performance behavior using microbenchmarks that we crafted for the purpose. We study the IPU's memory organization and performance. We study the latency and bandwidth that the on-chip and off-chip interconnects offer, both in point-to-point transfers and in a spectrum of collective operations, under diverse loads. We evaluate the IPU's compute power over matrix multiplication, convolution, and AI/ML primitives. We discuss actual performance in comparison with its theoretical limits. Our findings reveal how the IPU's architectural design affects its performance. Moreover, they offer simple mental models to predict an application's performance on the IPU, on the basis of the computation and communication steps it involves. This report is the natural extension to a novel architecture of a continuing effort of ours that focuses on the microbenchmark-based discovery of massively parallel architectures.

研究动机与目标

• 激发并证明研究 Graphcore IPU 架构的必要性
• 通过有针对性的微基准测试表征 IPU 的体系结构特征
• 提供可重复的实验条件，以促进对 IPU 行为的理解
• 提供可为研究者在面向 IPU 的性能分析中提供指导的观察结果

提出的方法

• 应用微基准测试技术探查 IPU 微架构组件
• 设计并执行一组微基准测试，以隔离计算、内存和互连行为
• 分析结果以推断 IPU 的体系结构特征
• 讨论实验设置和条件以实现可重复性
• 参考 Graphcore 提供用于测试的早期访问 IPU 系统

实验结果

研究问题

• RQ1 通过微基准测试揭示的 Graphcore IPU 的显著微架构特征有哪些？
• RQ2 在有针对性的工作负载下，IPU 组件（计算单元、内存、互连）如何表现？
• RQ3 在微基准测试下，IPU 的体系结构设计会带来哪些性能影响？
• RQ4 微基准测试结果在多大程度上可以推广到 IPU 硬件上的真实工作负载？

主要发现

• 研究结果基于作者研究的 IPU 架构的微基准测试结果
• 该文档表明通过早期访问测试系统对 IPU 进行了经验性检验
• 结果旨在在作者描述的实验条件下实现可重复性
• 工作承认外部因素可能的影响并强调客观分析
• 作为技术报告呈现，作者承认存在局限性