[论文解读] ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems

Suresh Nambi, Salim Ullah+4 more|arXiv (Cornell University)|Oct 24, 2020

Numerical Methods and Algorithms参考文献 37被引用 4

一句话总结

该论文提出ExPAN(N)D框架，结合Posit数表示与定点数运算，实现高效的FPGA人工智能推理。通过引入一种新型的Posit到定点数转换器及改进的参数存储方案，与8位定点数相比，模型存储量减少约46%，乘加（MAC）单元能耗降低约18%，且精度损失极小。

ABSTRACT

The recent advances in machine learning, in general, and Artificial Neural Networks (ANN), in particular, has made smart embedded systems an attractive option for a larger number of application areas. However, the high computational complexity, memory footprints, and energy requirements of machine learning models hinder their deployment on resource-constrained embedded systems. Most state-of-the-art works have considered this problem by proposing various low bit-width data representation schemes, optimized arithmetic operators' implementations, and different complexity reduction techniques such as network pruning. To further elevate the implementation gains offered by these individual techniques, there is a need to cross-examine and combine these techniques' unique features. This paper presents ExPAN(N)D, a framework to analyze and ingather the efficacy of the Posit number representation scheme and the efficiency of fixed-point arithmetic implementations for ANNs. The Posit scheme offers a better dynamic range and higher precision for various applications than IEEE $754$ single-precision floating-point format. However, due to the dynamic nature of the various fields of the Posit scheme, the corresponding arithmetic circuits have higher critical path delay and resource requirements than the single-precision-based arithmetic units. Towards this end, we propose a novel Posit to fixed-point converter for enabling high-performance and energy-efficient hardware implementations for ANNs with minimal drop in the output accuracy. We also propose a modified Posit-based representation to store the trained parameters of a network. Compared to an $8$-bit fixed-point-based inference accelerator, our proposed implementation offers $\approx46\%$ and $\approx18\%$ reductions in the storage requirements of the parameters and energy consumption of the MAC units, respectively.

研究动机与目标

• 为解决在资源受限的嵌入式系统中部署人工神经网络（ANNs）所面临的高计算、高内存和高能耗需求。
• 评估Posit数格式在神经网络推理中与IEEE 754单精度浮点数的对比效果。
• 通过将Posit算术转换为定点数表示，降低其硬件开销，实现高效的FPGA部署。
• 在显著减少模型参数存储量和MAC单元能耗的同时，最大限度减少精度下降。

提出的方法

• 提出一种新型的Posit到定点数转换器，将动态范围的Posit表示映射为适合FPGA部署的高效定点数运算。
• 引入一种改进的基于Posit的参数存储格式，以减少内存占用，同时不损害模型精度。
• 采用定点数算术单元进行推理计算，利用Posits的精度优势，同时避免其高面积和高延迟的算术电路。
• 通过转换后的定点数格式，优化MAC单元的硬件流水线与数据通路，提升能效。
• 利用FPGA原型设计评估基准神经网络在性能、面积和能效方面的表现。
• 结合网络剪枝与低精度算术技术，与Posit表示协同使用，以最大化系统级效率提升。

实验结果

研究问题

• RQ1 与8位定点数相比，Posit数表示是否能减少FPGA上人工神经网络的模型存储量和能耗？
• RQ2 在神经网络推理中，Posits的动态范围和精度与IEEE 754单精度浮点数相比如何？
• RQ3 Posit到定点数的转换在多大程度上可保持模型精度，同时降低硬件复杂度？
• RQ4 改进的基于Posit的参数存储格式对内存占用和能效的影响如何？
• RQ5 Posit表示与定点数算术的综合效应如何提升整体系统效率？

主要发现

• 所提出的Posit到定点数转换器可实现高性能且能效高的FPGA实现，且精度损失极小。
• 与8位定点数加速器相比，所提系统将参数存储需求减少了约46%。
• MAC单元的能耗比其8位定点数对应物降低了约18%。
• 改进的基于Posit的参数存储格式有效减少了内存占用，同时保持了模型精度。
• 该框架表明，将Posit表示与定点数算术结合，可在不牺牲推理精度的前提下，显著提升存储与能效效率。
• 通过硬件感知转换，缓解了Posits的动态特性，降低了FPGA实现中的关键路径延迟和资源使用量。