[论文解读] How to choose a decoder for a fault-tolerant quantum computer? The speed vs accuracy trade-off

Nicolas Delfosse, Andres Paz+2 more|arXiv (Cornell University)|Oct 23, 2023

Quantum Computing Algorithms and Architecture被引用 4

一句话总结

本文提出一种框架，通过平衡解码速度与准确性，并以时空成本为度量标准，选择容错量子计算机的最优解码器。该框架引入一种协议以优化解码器的停止时间，表明在台式机上运行的PyMatching可处理数千个逻辑T门，但对于10⁵个门可能因解码延迟而过慢，凸显了对硬件优化解码器的需求。

ABSTRACT

Achieving practical quantum advantage requires a classical decoding algorithm to identify and correct faults during computation. This classical decoding algorithm must deliver both accuracy and speed, but in what combination? When is a decoder "fast enough" or "accurate enough"? In the case of surface codes, tens of decoding algorithms have been proposed, with different accuracies and speeds. However, it has been unclear how to choose the best decoder for a given quantum architecture. Should a faster decoder be used at the price of reduced accuracy? Or should a decoder sacrifice accuracy to fit within a given time constraint? If a decoder is too slow, it may be stopped upon reaching a time bound, at the price of some time-out failures and an increased failure rate. What then is the optimal stopping time of the decoder? By analyzing the speed vs. accuracy tradeoff, we propose strategies to select the optimal stopping time for a decoder for different tasks. We design a protocol to select the decoder that minimizes the spacetime cost per logical gate, for logical computation of a given depth. Our protocol enables comparison of different decoders, and the selection of an appropriate decoder for a given fault-tolerant quantum computing architecture. We illustrate our protocol for the surface code equipped with a desktop implementation of the PyMatching decoder. We estimate PyMatching is fast enough to implement thousands of logical gates with a better accuracy than physical qubits. However, we find it is not sufficiently fast to reach 10^5 logical gates, under certain assumptions, due to the decoding delay which forces qubits to idle and accumulate errors while idling. We expect further improvements to PyMatching are possible by running it on a better machine or by reducing the OS interference.

研究动机与目标

• 为容错量子计算架构中如何选择解码器这一开放问题提供解答。
• 开发一种系统化方法，以最小化每个逻辑门的时空成本来选择解码器。
• 分析解码延迟对逻辑错误率与资源开销的影响。
• 在现实硬件约束下评估现有解码器（如PyMatching）的性能。
• 指导经典解码算法与量子硬件的协同设计，以实现可扩展的量子优势。

提出的方法

• 作者定义了一项时空成本度量，以考虑解码延迟与逻辑失败率。
• 他们通过配置可调停止时间的时间约束解码策略，对解码器速度与准确性之间的权衡进行建模。
• 该协议通过在不同逻辑门深度与物理错误率下模拟性能，对比不同解码器的表现。
• 他们将该框架应用于具有1 μs综合征提取时间与p = 10⁻³物理错误率的表面码。
• 他们在台式机上评估PyMatching以估算实际解码性能，并识别如操作系统干扰等瓶颈。
• 他们使用数值模拟，在不同逻辑门数量下比较线性时间、二次时间与即时解码器的性能。

Figure 1: State injection circuit for the implementation of a $T$ gate. Assume that we can prepare a $T$ state $|{T}\rangle=\frac{1}{\sqrt{2}}(|{0}\rangle+e^{i\pi/4}|{1}\rangle)$ on the bottom qubit. Then, we can apply a $T$ gate on the top qubit using only Clifford operations. The gate $S$ is appli

实验结果

研究问题

• RQ1 在容错量子计算中，为最小化时空成本，解码器的最佳停止时间是什么？
• RQ2 在表面码架构中，解码延迟如何影响逻辑错误率与资源成本？
• RQ3 对于给定数量的逻辑T门，哪种解码器在速度与准确性之间提供了最佳权衡？
• RQ4 在现实硬件约束下，现有解码软件（如PyMatching）能否扩展至大规模量子计算？
• RQ5 硬件层面因素（如操作系统干扰与计算架构）如何影响解码器性能？

主要发现

• 在台式机上运行的PyMatching可对数千个逻辑T门进行解码，其错误率低于物理量子比特，证明了中等规模计算的实际可行性。
• 当逻辑门数量超过10⁵时，PyMatching的解码延迟成为主要限制因素，导致因空闲量子比特错误累积而增加逻辑失败率。
• 对于小规模门数，线性时间解码器的时空成本比二次时间解码器高出最多4倍，但在大规模计算中可节省80%。
• 最优解码器的选择与逻辑T门数量之间呈非单调关系，表明解码器选择具有高度情境依赖性。
• PyMatching的运行时波动显著受操作系统干扰影响，表明专用硬件可提升稳定性和性能。
• 通过硬件加速（如FPGA或ASIC）或预解码技术（如BP或懒惰解码）进行未来改进，可减少解码延迟，从而支持更大规模的容错计算。

Figure 2: (a) Runtime distribution of PyMatching estimated using $10^{9}$ decoding trials for a distance-29 surface code with $d$ rounds of syndrome extraction on a desktop computer with an Intel Xeon CPU E5-2620 v4 @2.1Ghz processor with 64Gb of memory. We use Stim [ 23 ] to sample circuit faults a