[论文解读] Information Leakage Between FPGA Long Wires.

Ilias Giechaskiel, Ken Eguro|arXiv (Cornell University)|Nov 27, 2016

Physical Unclonable Functions (PUFs) and Hardware Security参考文献 13被引用 9

一句话总结

本文提出了一种新型FPGA隐蔽信道，利用相邻且未连接的长导线之间由串扰引起的延迟变化，其中携带逻辑'1'的导线会减少邻近导线的延迟。作者展示了可实际测量的信道，对相邻导线状态的推断准确率达99%，并实现了最高6 kbps的带宽，可在多个FPGA系列中复现。

ABSTRACT

Field-Programmable Gate Arrays (FPGAs) are integrated circuits that implement reconfigurable hardware. They are used in modern systems as they are well-suited for creating specialized, highly-optimized integrated circuits without the need to design and manufacture dedicated chips. As the capacity of FPGAs grows, it is increasingly common for designers to incorporate implementations of algorithms and protocols from a range of third-party sources. The monolithic nature of FPGAs means that all on-chip circuits, including third party black-box designs, must share common on-chip infrastructure, such as routing resources. In this paper, we present a covert channel based on a previously unexplored source of information leakage that occurs between adjacent but unconnected, so called wires, on the FPGA chip. We observe that a long wire carrying a logical 1 reduces the delay of nearby wires and that the delay decreases linearly with the length of wires used. This effect leads to a covert channel that can be used for both covert communication between circuits, and for exfiltration of secrets from the chip. We show that the effect is measurable for both static and dynamic signals, and that it can be detected using very small on-board circuits. In our prototype, we are able to correctly infer the logical state of an adjacent long wire over 99% of the time, even without error correction, and for signals that are maintained for as little as $82\mu s$. Using a simple encoding scheme, our covert channel bandwidth is as high as 6kbps. We characterize the covert channel in detail and show that it can be replicated on different generations and families of devices (Virtex 5, Virtex 6, and Artix 7), with different configurations, and is measurable even when multiple competing circuits are present.

研究动机与目标

• 研究FPGA中相邻且未连接的长导线之间此前未被探索的信息泄露。
• 识别并利用串扰引起的延迟变化作为隐蔽通信的来源。
• 展示一种实际且可测量的隐蔽信道，用于FPGA系统中的秘密数据外泄或电路间通信。
• 评估该信道在不同FPGA器件系列和配置下的鲁棒性与可扩展性。

提出的方法

• 测量携带逻辑'1'状态的长导线引起的邻近导线延迟变化，利用导线长度与延迟减少之间的线性关系。
• 设计最小化片上电路以检测并解码由邻近长导线引起的延迟变化。
• 实施简单的编码方案，通过观测到的延迟变化调制数据，实现隐蔽通信。
• 在不同FPGA系列（Virtex 5、Virtex 6、Artix 7）中，于不同配置和竞争电路负载下验证该信道。
• 使用统计分析，基于测量到的延迟偏移高精度推断邻近导线的逻辑状态。

实验结果

研究问题

• RQ1 能否利用长导线引起的延迟变化作为FPGA中隐蔽通信信道？
• RQ2 能否通过延迟测量高精度推断邻近长导线的逻辑状态？
• RQ3 此类隐蔽信道在真实FPGA硬件中可实现的最大带宽是多少？
• RQ4 该效应是否在不同FPGA器件系列中持续存在，并在并发电路活动下依然有效？

主要发现

• 邻近导线的延迟随携带逻辑'1'的相邻长导线长度线性减少。
• 该隐蔽信道在未使用纠错机制的情况下，对邻近长导线状态的推断准确率达99%。
• 该信道可测量的信号最短可达82 μs，能够检测瞬态状态。
• 通过简单编码方案，该隐蔽信道最高可实现6 kbps的带宽。
• 该效应在多个FPGA系列中一致可测量，包括Virtex 5、Virtex 6和Artix 7。
• 即使在FPGA上存在多个竞争电路活动时，该信道仍可被检测到。