[论文解读] Joint Channel Estimation and Data Decoding using SVM-based Receivers.

Sami Akın, Maxim Penner+1 more|arXiv (Cornell University)|Dec 4, 2020

Wireless Signal Modulation Classification参考文献 19被引用 4

一句话总结

本文提出一种基于支持向量机（SVM）的联合信道估计算法与数据解码接收机，将导频辅助的信道估计、解调和译码整合到统一的SVM框架中。结果表明，SVM接收机的性能接近最大似然译码，且即使在使用1-bit ADC输出训练时，也优于传统的分块处理接收机。

ABSTRACT

Modern communication systems organize receivers in blocks in order to simplify their analysis and design. However, an approach that considers the receiver design from a wider perspective rather than treating it block-by-block may take advantage of the impacts of these blocks on each other and provide better performance. Herein, we can benefit from machine learning and compose a receiver model implementing supervised learning techniques. With this motivation, we consider a one-to-one transmission system over a flat fast fading wireless channel and propose a support vector machines (SVM)-based receiver that combines the pilot-based channel estimation, data demodulation and decoding processes in one joint operation. We follow two techniques in the receiver design. We first design one SVM-based classifier that outputs the class of the encoding codeword that enters the encoder at the transmitter side. Then, we put forward a model with one SVM-based classifier per one bit in the encoding codeword, where each classifier assigns the value of the corresponding bit in the encoding vector. With the second technique, we simplify the receiver design especially for longer encoding codewords. We show that the SVM-based receiver performs very closely to the maximum likelihood decoder, which is known to be the optimal decoding strategy when the encoding vectors at the transmitter are equally likely. We further show that the SVM-based receiver outperforms the conventional receivers that perform channel estimation, data demodulation and decoding in blocks. Finally, we show that we can train the SVM-based receiver with 1-bit analog-to-digital converter (ADC) outputs and the SVM-based receiver can perform very closely to the conventional receivers that take 32-bit ADC outputs as inputs.

研究动机与目标

• 通过将信道估计、解调和译码整合到统一框架中，克服现代通信系统中分块处理接收机设计的局限性。
• 利用监督学习，特别是SVM，通过利用块间依赖关系来提升接收机性能。
• 设计一种即使在低分辨率ADC（如1-bit量化）下也能保持高性能的接收机。
• 通过使用逐比特SVM分类器而非全码字分类，简化长码字的接收机复杂度。
• 证明基于SVM的接收机可逼近最优最大似然译码的性能。

提出的方法

• 设计一个单一SVM分类器，输出所传输编码码字的类别，将整个码字视为单一分类任务。
• 提出一种替代模型，即每个码字比特对应一个SVM分类器，以实现对更长码字的可扩展设计。
• 使用已知导频符号和传输码字生成的带标签训练数据来训练SVM接收机。
• 将1-bit模数转换器（ADC）输出作为SVM的输入特征，以降低硬件复杂度。
• 将联合估计与译码问题建模为监督学习任务，使SVM学习从接收信号到传输码字的映射关系。
• 在SVM中应用核方法，以处理快衰落信道中的非线性信号失真。

实验结果

研究问题

• RQ1 基于SVM的联合接收机在误比特率方面是否优于传统的分块处理接收机？
• RQ2 在1-bit ADC输出上训练的接收机，其性能在多大程度上可与使用32-bit ADC输入的传统接收机相匹配？
• RQ3 逐比特SVM分类器模型是否在保持高精度的同时显著降低了长码字的复杂度？
• RQ4 基于SVM的接收机在多大程度上可逼近最优最大似然译码器的性能？
• RQ5 通过统一的SVM接收机架构，能否有效利用块间依赖关系？

主要发现

• 基于SVM的接收机性能非常接近最大似然译码器，后者是等概率码字的最优基准。
• 所提出的接收机优于传统分块处理接收机，后者依次执行信道估计、解调和译码。
• 在1-bit ADC输出上训练的SVM接收机性能几乎与使用32-bit ADC输入的传统接收机相当，证明了其对低分辨率量化具有鲁棒性。
• 逐比特SVM分类器模型显著简化了接收机设计，尤其适用于长编码码字，且未牺牲性能。
• 联合SVM接收机有效利用了块间依赖关系，与独立块处理相比，显著改善了误码率性能。