[论文解读] MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning

Yao Lai, Yao Mu+1 more|arXiv (Cornell University)|Nov 24, 2022

Advanced Memory and Neural Computing被引用 21

一句话总结

MaskPlace 将芯片放置重新定义为像素级视觉表示学习，并使用带密集奖励的 RL 策略在 224x224 画布上放置宏块，实现 0% 重叠的有效布局，相较于现有方法在布线长度方面有显著减少。

ABSTRACT

Placement is an essential task in modern chip design, aiming at placing millions of circuit modules on a 2D chip canvas. Unlike the human-centric solution, which requires months of intense effort by hardware engineers to produce a layout to minimize delay and energy consumption, deep reinforcement learning has become an emerging autonomous tool. However, the learning-centric method is still in its early stage, impeded by a massive design space of size ten to the order of a few thousand. This work presents MaskPlace to automatically generate a valid chip layout design within a few hours, whose performance can be superior or comparable to recent advanced approaches. It has several appealing benefits that prior arts do not have. Firstly, MaskPlace recasts placement as a problem of learning pixel-level visual representation to comprehensively describe millions of modules on a chip, enabling placement in a high-resolution canvas and a large action space. It outperforms recent methods that represent a chip as a hypergraph. Secondly, it enables training the policy network by an intuitive reward function with dense reward, rather than a complicated reward function with sparse reward from previous methods. Thirdly, extensive experiments on many public benchmarks show that MaskPlace outperforms existing RL approaches in all key performance metrics, including wirelength, congestion, and density. For example, it achieves 60%-90% wirelength reduction and guarantees zero overlaps. We believe MaskPlace can improve AI-assisted chip layout design. The deliverables are released at https://laiyao1.github.io/maskplace.

研究动机与目标

• 推动自动化芯片放置以高效处理数百万个模块并确保有效布局。
• 引入像素级视觉表示，以在大画布上对网表和引脚配置进行编码。
• 开发能够产生密集奖励的强化学习策略，在确保不重叠的同时优化线长。
• 实现对整画布（224x224）的放置，具有大的动作空间和高效的计算。
• 在公开基准上展示相较于现有优化型和学习型放置方法的优越性。

提出的方法

• 将放置表示为一个马尔可夫决策过程（Markov Decision Process），每次放置一个模块。
• 使用三种像素级掩模（位置、线网、视图）来编码状态并在不丢失引脚级信息的前提下实现学习。
• 通过策略网络中的1x1卷积融合掩模，预测画布上的密集动作概率图。
• 定义基于每步部分HPWL下降的密集奖励，以在没有稀疏奖励的情况下引导学习。
• 加入拥塞满意度模块，在动作选择阶段强制满足硬性拥塞约束。
• 使用PPO2 actor-critic框架进行训练，以HPWL作为主要奖励，并在最终动作选择步骤引入拥塞感知。

实验结果

研究问题

• RQ1 像素级的芯片网表和引脚的视觉表示是否能在大画布上支持高质量、非重叠的宏块放置？
• RQ2 在RL框架中，基于密集HPWL奖励的设计是否优于稀疏奖励或超图表示的芯片放置？
• RQ3 与最新的优化型和学习型放置方法相比，MaskPlace在布线长度、拥塞和密度等标准基准上表现如何？
• RQ4 在合理的计算时间内，在完整的224x224画布上实现零重叠放置与有竞争力的布线指标是否可行？

主要发现

• MaskPlace 在评估基准上始终实现0%重叠。
• 与Graph Placement和DeepPR相比，MaskPlace在布线长度方面有显著下降（在某些比较中下降幅度可达60%-90%）。
• 在24个公开基准上，MaskPlace在布线长度、拥塞和密度等指标上优于最近的RL和优化方法。
• 与Graph Placement比较时，MaskPlace在大多数ISPD基准上展示出显著的HPWL提升和零重叠。
• MaskPlace在完整的224x224画布上运行，具有高分辨率表示，并在推理速度上优于若干竞争的学习型方法。
• 拥塞满足机制确保在保持线长高效优化的同时满足硬性密度约束。