[论文解读] Massive MIMO with Arbitrary Non-Ideal Arrays: Hardware Scaling Laws and Circuit-Aware Design

Emil Björnson, Michail Matthaiou+1 more|arXiv (Cornell University)|Jan 1, 2014

Advanced MIMO Systems Optimization被引用 13

一句话总结

本文针对具有任意非理想阵列的大规模MIMO系统建立了硬件缩放律，证明了即使存在相位漂移和加性失真等硬件非理想因素，用户速率仍保持鲁棒。研究表明，通过电路感知设计，电路功耗可实现√N而非线性地随N增长，从而实现大规模阵列的成本效益部署。

ABSTRACT

Massive multiple-input multiple-output (MIMO) systems are cellular networks where the base stations (BSs) are equipped with unconventionally many antennas, deployed on co-located or distributed arrays. Huge spatial degrees-of-freedom are achieved by coherent processing over these massive arrays, which provide strong signal gains, resilience to imperfect channel knowledge, and low interference. This comes at the price of more infrastructure; the hardware cost and circuit power consumption scale linearly/affinely with the number of BS antennas $N$. Hence, the key to cost-efficient deployment of large arrays is low-cost antenna branches with low circuit power, in contrast to today's conventional expensive and power-hungry BS antenna branches. Such low-cost transceivers are prone to hardware imperfections, but it has been conjectured that the huge degrees-of-freedom would bring robustness to such imperfections. We prove this claim for a generalized uplink system with multiplicative phase-drifts, additive distortion noise, and noise amplification. Specifically, we derive closed-form expressions for the user rates and a scaling law that shows how fast the hardware imperfections can increase with $N$ while maintaining high rates. The connection between this scaling law and the power consumption of different transceiver circuits is rigorously exemplified. This reveals that one can make the circuit power increase as $\sqrt{N}$, instead of linearly, by careful circuit-aware system design.

研究动机与目标

• 研究硬件非理想性（如相位漂移、加性失真和噪声放大）对具有任意非理想阵列的大规模MIMO系统的影响。
• 确定上行链路大规模MIMO系统中硬件不完善性与系统性能之间的基本权衡。
• 推导出量化硬件非理想性随天线数N增长速度的缩放律，同时保持高 spectral efficiency。
• 将这些缩放律与实际电路功耗关联，实现低功耗、低成本收发器设计。

提出的方法

• 推导出具有乘法相位漂移和加性失真噪声的一般化上行链路大规模MIMO系统中用户速率的闭式表达式。
• 在大规模阵列上采用相干处理以利用空间自由度并缓解信道不确定性。
• 建立缩放律，表明只要保持高谱效率，硬件非理想性可与√N成比例增长。
• 将推导出的缩放律与不同收发器电路的功耗关联，实现电路感知的系统设计。
• 通过数学分析证明，通过优化硬件设计，电路功耗可实现√N而非线性地随N增长。
• 考虑包含噪声放大和非理想元件的实用模型，以反映实际部署约束。

实验结果

研究问题

• RQ1 在具有任意非理想阵列的大规模MIMO系统中，相位漂移和加性失真等硬件非理想性如何影响用户速率？
• RQ2 在保持高谱效率的前提下，硬件不完善性随天线数N的最大增长速率是多少？
• RQ3 能否通过智能系统设计将电路功耗从线性缩放降低为次线性缩放？
• RQ4 推导出的缩放律与大规模MIMO系统中实际收发器电路功耗之间有何关联？

主要发现

• 由于大规模MIMO中存在大量空间自由度，相位漂移和加性失真等硬件非理想性可随√N增长，同时保持高用户速率。
• 系统对硬件非理想性表现出鲁棒性能，证实了大规模阵列天然抑制非理想硬件效应的猜想。
• 通过电路感知的系统设计，电路功耗可从线性缩放（O(N)）降低至√N缩放（O(√N)）。
• 推导出的缩放律为大规模MIMO部署中硬件质量与系统成本之间的平衡提供了定量设计指导。
• 闭式速率表达式使得在实际硬件约束下能够实现精确的性能评估与优化。
• 结果表明，当与适当的系统级设计相结合时，低成本、低功耗收发器在大规模MIMO中是可行的。