[论文解读] Novel Reversible Multiplier Architecture Using Reversible TSG Gate

Himanshu Thapliyal, M. B. Srinivas|ArXiv.org|May 1, 2006

Quantum Computing Algorithms and Architecture参考文献 6被引用 5

一句话总结

该论文提出了一种基于可逆TSG门的新型N×N可逆乘法器架构，利用其作为全加器的单一门功能。通过结合使用Fredkin门并行生成部分积，以及基于TSG的可逆并行加法器实现对数级减少，该设计在可逆门数量和垃圾输出方面相比先前的可逆乘法器实现了显著优化。

ABSTRACT

In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. Recently a 4 * 4 reversible gate called TSG is proposed. The most significant aspect of the proposed gate is that it can work singly as a reversible full adder, that is reversible full adder can now be implemented with a single gate only. This paper proposes a NXN reversible multiplier using TSG gate. It is based on two concepts. The partial products can be generated in parallel with a delay of d using Fredkin gates and thereafter the addition can be reduced to log2N steps by using reversible parallel adder designed from TSG gates. Similar multiplier architecture in conventional arithmetic (using conventional logic) has been reported in existing literature, but the proposed one in this paper is totally based on reversible logic and reversible cells as its building block. A 4x4 architecture of the proposed reversible multiplier is also designed. It is demonstrated that the proposed multiplier architecture using the TSG gate is much better and optimized, compared to its existing counterparts in literature; in terms of number of reversible gates and garbage outputs. Thus, this paper provides the initial threshold to building of more complex system which can execute more complicated operations using reversible logic.

研究动机与目标

• 设计一种仅使用可逆逻辑元件的完全可逆乘法器架构，适用于低功耗和量子计算应用。
• 解决传统可逆乘法器依赖多种门且产生高垃圾输出的局限性。
• 利用TSG门的独特能力，作为可逆全加器，最小化硬件复杂度。
• 与现有设计相比，优化乘法器在可逆门数量和垃圾输出数量方面的表现。
• 为构建更复杂的可逆算术电路奠定基础，采用统一且高效的门级构建模块。

提出的方法

• 以TSG门作为基本构建模块，其可作为单个门的可逆全加器使用。
• 使用Fredkin门并行生成部分积，将部分积生成延迟降低至d个时间单位。
• 采用基于TSG门的分层可逆并行加法器结构，将加法步骤数减少至log₂N。
• 将乘法器构建为部分积生成与减少阶段的级联结构，全部使用可逆逻辑。
• 设计一个4×4可逆乘法器原型，以验证架构并测量性能指标。
• 通过保持输入和输出引脚数量相同，确保所有操作可逆，最小化垃圾输出。

实验结果

研究问题

• RQ1 能否仅使用TSG门作为基本组件设计出可逆乘法器，从而消除对多种门类型的需求？
• RQ2 将TSG门用作全加器对可逆乘法器的整体门数和垃圾输出有何影响？
• RQ3 与传统可逆加法器设计相比，使用基于TSG的并行加法器在延迟和硬件复杂度方面有何性能提升？
• RQ4 所提出的架构是否能在可逆门数量和垃圾输出方面优于现有可逆乘法器？
• RQ5 TSG门作为全加器的能力在多大程度上可简化复杂可逆算术电路的设计？

主要发现

• 所提出的4×4可逆乘法器在可逆门数量方面相比现有设计实现了显著减少。
• 该架构产生的垃圾输出少于先前的可逆乘法器，提升了效率和可扩展性。
• 使用TSG门作为全加器，可构建门数最少、延迟最优的可逆并行加法器。
• 部分积生成阶段以并行方式运行，延迟为d，提升了整体吞吐量。
• 通过基于TSG的加法器对部分积进行对数级减少，将加法步骤数减少至log₂N，优化了关键路径。
• 该设计表明，TSG门是构建复杂可逆算术电路的高效构建模块，为未来研究设立了新基准。