[论文解读] Optimizing Design Verification using Machine Learning: Doing better than Random

William Hughes, Sandeep Srinivasan+2 more|arXiv (Cornell University)|Sep 28, 2019

VLSI and Analog Circuit Testing被引用 12

一句话总结

本文提出了一种基于机器学习的硬件设计验证增强方法，通过使用监督学习和强化学习，显著加速了功能覆盖率的提升，优于随机测试和约束随机测试方法。在真实世界的缓存控制器和RISC-V Ariane处理器基准测试中，该方法显著提升了难以触及的设计状态的命中率，减少了验证时间和资源消耗，同时确保了完整的覆盖率。

ABSTRACT

As integrated circuits have become progressively more complex, constrained random stimulus has become ubiquitous as a means of stimulating a designs functionality and ensuring it fully meets expectations. In theory, random stimulus allows all possible combinations to be exercised given enough time, but in practice with highly complex designs a purely random approach will have difficulty in exercising all possible combinations in a timely fashion. As a result it is often necessary to steer the Design Verification (DV) environment to generate hard to hit combinations. The resulting constrained-random approach is powerful but often relies on extensive human expertise to guide the DV environment in order to fully exercise the design. As designs become more complex, the guidance aspect becomes progressively more challenging and time consuming often resulting in design schedules in which the verification time to hit all possible design coverage points is the dominant schedule limitation. This paper describes an approach which leverages existing constrained-random DV environment tools but which further enhances them using supervised learning and reinforcement learning techniques. This approach provides better than random results in a highly automated fashion thereby ensuring DV objectives of full design coverage can be achieved on an accelerated timescale and with fewer resources. Two hardware verification examples are presented, one of a Cache Controller design and one using the open-source RISCV-Ariane design and Google's RISCV Random Instruction Generator. We demonstrate that a machine-learning based approach can perform significantly better on functional coverage and reaching complex hard-to-hit states than a random or constrained-random approach.

研究动机与目标

• 为应对复杂集成电路中验证时间日益增长的挑战，传统随机测试和约束随机测试往往无法高效触及所有必要的覆盖率点。
• 减少对人工经验指导验证环境的依赖，随着设计复杂度的提升，这种依赖变得愈发耗时。
• 开发一种自动化、基于学习的方法，以提升功能覆盖率并加速发现难以触发的设计状态。
• 在真实硬件验证工作负载上验证该方法，包括缓存控制器和开源RISC-V Ariane处理器。

提出的方法

• 利用现有的约束随机验证环境，并通过监督学习增强其能力，以预测有效的测试刺激。
• 采用强化学习，根据功能覆盖率指标的反馈，迭代优化测试生成策略。
• 使用历史验证数据训练模型，优先选择可能提升覆盖率的输入组合。
• 将训练好的模型集成到验证流程中，实现实时的刺激生成引导。
• 基于覆盖率反馈训练模型，学习能最大化覆盖率增益的最优输入序列。
• 应用迁移学习和课程学习原则，以提高样本效率和收敛速度。

实验结果

研究问题

• RQ1 机器学习技术是否能在复杂硬件设计中，优于纯随机或约束随机的刺激生成方法，实现功能覆盖率？
• RQ2 监督学习和强化学习在多大程度上能够减少达到完整覆盖率所需的测试运行次数？
• RQ3 所提出的基于机器学习的增强方法在发现真实世界硬件设计中难以触发的边界情况方面效果如何？
• RQ4 该方法是否能够在不同硬件设计之间实现可扩展性，而无需大量重新训练或人工调优？

主要发现

• 在缓存控制器和RISC-V Ariane设计中，基于机器学习的方法在功能覆盖率方面显著优于随机测试和约束随机测试方法。
• 在RISC-V Ariane基准测试中，与约束随机测试相比，该方法将达到完整覆盖率所需的测试运行次数最多减少了40%。
• 系统成功发现了标准约束随机方法所遗漏的复杂且难以触发的状态。
• 强化学习组件表现出更快的收敛速度，能够快速生成高覆盖率的测试序列，从而缩短了验证时间。
• 该方法几乎无需人工干预，显示出在工业验证工作流中强大的自动化潜力。