[论文解读] Transceiver Design with Low-Precision Analog-to-Digital Conversion : An Information-Theoretic Perspective

Jaspreet Singh, Onkar Dabeer+1 more|ArXiv.org|Apr 8, 2008

Analog and Mixed-Signal Circuit Design参考文献 38被引用 8

一句话总结

本文研究了在低精度模数转换（ADC）下数字通信系统的根本容量极限，表明即使在20 dB信噪比下，2–3比特ADC也仅造成10–20%的频谱效率损失。研究证明，K级ADC的最优输入分布最多具有K+1个质量点，而对于1比特对称ADC，所有信噪比水平下二元反相调制均为最优。

ABSTRACT

Modern communication receiver architectures center around digital signal processing (DSP), with the bulk of the receiver processing being performed on digital signals obtained after analog-to-digital conversion (ADC). In this paper, we explore Shannon-theoretic performance limits when ADC precision is drastically reduced, from typical values of 8-12 bits used in current communication transceivers, to 1-3 bits. The goal is to obtain insight on whether DSP-centric transceiver architectures are feasible as communication bandwidths scale up, recognizing that high-precision ADC at high sampling rates is either unavailable, or too costly or power-hungry. Specifically, we evaluate the communication limits imposed by low-precision ADC for the ideal real discrete-time Additive White Gaussian Noise (AWGN) channel, under an average power constraint on the input. For an ADC with K quantization bins (i.e., a precision of log2 K bits), we show that the Shannon capacity is achievable by a discrete input distribution with at most K + 1 mass points. For 2-bin (1-bit) symmetric ADC, this result is tightened to show that binary antipodal signaling is optimum for any signal-to-noise ratio (SNR). For multi-bit ADC, the capacity is computed numerically, and the results obtained are used to make the following encouraging observations regarding system design with low-precision ADC : (a) even at moderately high SNR of up to 20 dB, 2-3 bit quantization results in only 10-20% reduction of spectral efficiency, which is acceptable for large communication bandwidths, (b) standard equiprobable pulse amplitude modulation with ADC thresholds set to implement maximum likelihood hard decisions is asymptotically optimum at high SNR, and works well at low to moderate SNRs as well.

研究动机与目标

• 确定在高带宽系统中，低精度ADC所施加的根本通信性能极限。
• 分析由于有限分辨率ADC导致输出量化时的AWGN信道容量。
• 在平均功率约束下，识别最优输入分布和量化器设计。
• 评估低精度ADC导致的频谱效率损失，并评估其在未来的高带宽系统中的可接受性。

提出的方法

• 使用信息论框架，对K级ADC引起的输出量化AWGN信道进行建模。
• 应用Dubins定理，证明K级量化器的最优输入分布最多具有K+1个质量点。
• 推导容量问题的对偶形式，以计算多比特ADC的紧致上界。
• 采用切平面算法，数值计算近似最优的输入分布和量化器阈值。
• 同时考虑对称与非对称量化器设计，对输入分布和量化器参数进行联合优化。
• 通过数值计算2比特和3比特ADC的容量与频谱效率，验证结果。

实验结果

研究问题

• RQ1 在AWGN信道中使用1–3比特ADC时，可实现的最大频谱效率是多少？
• RQ2 低精度ADC的最优输入分布是否可表征为有限支撑？若是，需要多少个质量点？
• RQ3 在所有信噪比水平下，1比特对称ADC是否均以二元反相调制为最优？
• RQ4 与未量化接收相比，使用低精度ADC导致的频谱效率损失有多大？
• RQ5 标准PAM调制配合最大似然硬判决阈值能否实现近似最优性能？

主要发现

• 对于K级ADC，最优输入分布最多具有K+1个质量点，数值结果表明K个质量点已足够。
• 对于1比特对称ADC，无论信噪比如何，二元反相调制均为最优，证明其根本最优性。
• 在0 dB信噪比下，2比特ADC可实现未量化系统95%的频谱效率。
• 在20 dB信噪比下，3比特ADC可实现未量化系统85%的频谱效率，表明仅损失15%。
• 标准等概率PAM配合最大似然硬判决阈值的性能，几乎与数值优化的输入分布和量化器设计相当。
• 在平均功率约束下，达到容量的输入分布具有有界支撑，这是由量化所隐含的峰值功率约束所导致。