[论文解读] Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms

Kevin K. Chang, A. Giray Yağlıkçı+8 more|arXiv (Cornell University)|May 29, 2017

Parallel Computing and Optimization Techniques参考文献 104被引用 6

一句话总结

本文提出 Voltron，一种通过动态增加关键 DRAM 操作（激活、恢复、预充电）的延迟，将 DRAM 供电电压大幅降低至标称值以下的机制，使 DRAM 平均功耗降低 10.5%，系统功耗降低 7.3%，同时在内存密集型工作负载下仅造成 1.8% 的平均性能损失。

ABSTRACT

The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a thorough understanding of the effect voltage scaling has on DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by DRAM standards. Using an FPGA-based testing platform, we perform an experimental study of 124 real DDR3L (low-voltage) DRAM chips manufactured recently by three major DRAM vendors. We find that reducing the supply voltage below a certain point introduces bit errors in the data, and we comprehensively characterize the behavior of these errors. We discover that these errors can be avoided by increasing the latency of three major DRAM operations (activation, restoration, and precharge). We perform detailed DRAM circuit simulations to validate and explain our experimental findings. We also characterize the various relationships between reduced supply voltage and error locations, stored data patterns, DRAM temperature, and data retention. Based on our observations, we propose a new DRAM energy reduction mechanism, called Voltron. The key idea of Voltron is to use a performance model to determine by how much we can reduce the supply voltage without introducing errors and without exceeding a user-specified threshold for performance loss. Voltron reduces the average system energy by 7.3% while limiting the average system performance loss to only 1.8%, for a variety of workloads.

研究动机与目标

• 解决现代计算系统中 DRAM 功耗的关键挑战，尤其是在数据中心和移动平台中的应用。
• 研究将 DRAM 供电电压降低至标称值以下对可靠性、延迟和数据保持时间的影响。
• 表征真实 DDR3L DRAM 芯片中电压缩放、误码率和操作延迟之间的权衡关系。
• 开发一种实用机制，实现在不牺牲数据完整性或造成过度性能损失的前提下实现激进的电压缩放。
• 提出并评估 Voltron，一种基于性能约束优化电压缩放的新能效降低机制。

提出的方法

• 构建基于 FPGA 的测试平台，精确控制并调节来自三家厂商的 124 颗真实 DDR3L 芯片的 DRAM 供电电压。
• 对降低电压下的位错误、错误位置、数据模式、温度影响和数据保持时间进行了广泛实验表征。
• 发现增加激活、恢复和预充电操作的延迟可消除电压引起的位错误。
• 开发分段线性性能模型，以预测在不同电压和延迟配置下的系统性能损失。
• 设计 Voltron，使其动态选择在性能损失控制在用户定义阈值范围内的最低可能阵列供电电压。
• 将 DRAM 阵列（降低）与外围电路（标称）的电压缩放分离，以保持高内存通道频率。

实验结果

研究问题

• RQ1 降低 DRAM 供电电压与现代 DDR3L 芯片中位错误发生之间的关系是什么？
• RQ2 误码率如何随供电电压降低而变化？数据模式、温度和错误位置在其中起什么作用？
• RQ3 增加基本 DRAM 操作（激活、恢复、预充电）的延迟是否能消除电压引起的错误？
• RQ4 在激进降低 DRAM 供电电压时，能耗节省与性能损失之间的最优权衡是什么？
• RQ5 与现有 DRAM 动态电压频率缩放（DVFS）机制相比，Voltron 在能效和性能方面表现如何？

主要发现

• 将 DRAM 供电电压降低至标称值以下会导致位错误，且当电压低于最小可靠电压 $V_{\text{min}}$ 时，错误率呈指数级增长。
• 增加激活、恢复和预充电操作的延迟可消除电压引起的位错误，从而支持进一步的电压缩放。
• Voltron 在一系列四核内存密集型工作负载下，使平均 DRAM 能耗降低 10.5%，系统能耗降低 7.3%。
• Voltron 导致的平均系统性能损失仅为 1.8%，远在大多数应用可接受的范围内。
• Voltron 在能效方面显著优于以往的 DRAM 动态电压频率缩放机制。
• 研究发现，错误模式对存储的数据模式、温度和 DRAM 芯片内部物理位置敏感，某些位位置和高温条件下更容易发生错误。