[论文解读] Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance

Oğuzhan Canpolat, A. Giray Yağlıkçı+4 more|arXiv (Cornell University)|Jun 27, 2024

Advanced Data Storage Technologies被引用 4

一句话总结

本文对DDR5中首个针对读取干扰的行级缓解机制——每行激活计数（PRAC）进行了首次严格分析。PRAC通过使用退避信号仅在需要时触发刷新，从而降低性能开销，但在未来DRAM芯片上仍可能带来高达63.2%的性能开销，并可能被用于内存性能攻击，而当$N_{RH} \geq 10$时仍保持安全。

ABSTRACT

We present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting (PRAC), described in JEDEC DDR5 specification's April 2024 update. Unlike prior state-of-the-art that advises the memory controller to periodically issue refresh management (RFM) commands, which provides the DRAM chip with time to perform refreshes, PRAC introduces a new back-off signal. PRAC's back-off signal propagates from the DRAM chip to the memory controller and forces the memory controller to 1) stop serving requests and 2) issue RFM commands. As a result, RFM commands are issued when needed as opposed to periodically, reducing RFM's overheads. We analyze PRAC in four steps. First, we define an adversarial access pattern that represents the worst-case for PRAC's security. Second, we investigate PRAC's configurations and security implications. Our analyses show that PRAC can be configured for secure operation as long as no bitflip occurs before accessing a memory location 10 times. Third, we evaluate the performance impact of PRAC and compare it against prior works using Ramulator 2.0. Our analysis shows that while PRAC incurs less than 13% performance overhead for today's DRAM chips, its performance overheads can reach up to 94% for future DRAM chips that are more vulnerable to read disturbance bitflips. Fourth, we define an availability adversarial access pattern that exacerbates PRAC's performance overhead to perform a memory performance attack, demonstrating that such an adversarial pattern can hog up to 94% of DRAM throughput and degrade system throughput by up to 95%. We discuss PRAC's implications on future systems and foreshadow future research directions. To aid future research, we open-source our implementations and scripts at https://github.com/CMU-SAFARI/ramulator2.

研究动机与目标

• 分析PRAC在DDR5中作为最先进的DRAM读取干扰缓解技术，在安全性、性能、能效和成本方面的综合影响。
• 评估PRAC在最大化行激活计数的对抗性访问模式下防止位翻转的有效性。
• 量化PRAC在现代及未来DRAM技术中的性能与能效开销。
• 探究PRAC是否可被用作内存性能攻击的攻击向量。
• 识别提升PRAC效率并增强其对抗滥用能力的研究方向。

提出的方法

• 提出一种面向安全的对抗性访问模式，以在PRAC保护下最大化行激活计数，模拟最坏情况威胁场景。
• 采用周期精确仿真，使用扩展了DRAMPower的Ramulator 2.0，评估60种多工作负载组合下的性能与能效开销。
• 引入一种面向可用性的对抗性模式，以在高激活率下压力测试PRAC的性能表现。
• 分析PRAC的退避信号机制，该机制仅在激活计数达到临界阈值时触发内存控制器干预。
• 通过确定PRAC防止位翻转所需的最小$N_{RH}$（最小锤击次数）来评估其安全性。
• 使用开源仿真基础设施（可在https://github.com/CMU-SAFARI/ramulator2获取）以确保可复现性，并支持未来研究。

Figure 1 : Maximum activations to a row allowed by (a) PRFM and (b) PRAC -N

实验结果

研究问题

• RQ1 在PRAC保护下，DRAM行的最大激活计数能达到多少？其值如何随不同PRAC配置而变化？
• RQ2 在现代及未来DRAM芯片上，PRAC在良性与对抗性工作负载下的性能与能效开销是多少？
• RQ3 PRAC是否可通过耗尽DRAM吞吐量来被用于发起内存性能攻击？
• RQ4 在对抗性行锤击攻击下，PRAC在何种最小$N_{RH}$值下可确保安全，防止位翻转？
• RQ5 哪些系统级优化可缓解PRAC的性能与能效开销？如何增强其对抗滥用的能力？

主要发现

• 只要在内存行被访问10次之前未发生位翻转，PRAC即可安全配置，确保$N_{RH} \geq 10$时的安全性。
• 在现代DRAM芯片上，PRAC在良性工作负载下最多带来13.4%的系统性能开销和23.0%的DRAM能效开销。
• 对于未来读取干扰更敏感的DRAM芯片，PRAC在60种工作负载下的平均性能开销升至48.5%（最高达63.2%）。
• 对抗性访问模式可利用PRAC消耗高达79%的DRAM吞吐量，并使系统吞吐量最多下降65%（平均下降53%），表明其具备作为性能攻击向量的潜力。
• 由于PRAC引入的$t_{RP}$和$t_{RC}$时序参数增加，即使在高$N_{RH}$值下也带来了不可忽视的性能开销，表明需要进行电路级优化。
• PRAC的退避机制相比周期性RFM可减少不必要的刷新，但其对控制器干预的依赖也带来了新的攻击面和性能瓶颈。

Figure 2 : Performance impact of evaluated read disturbance mitigation mechanisms on 60 benign four-core workloads