[Paper Review] Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency

Kevin K. Chang, A. Giray Yağlıkçı+8 more|arXiv (Cornell University)|May 8, 2018

Low-power high-performance VLSI design51 references4 citations

TL;DR

Voltron is a runtime DRAM energy optimization mechanism that aggressively reduces array supply voltage below nominal levels while maintaining reliability by dynamically increasing latency of key DRAM operations (activation, precharge, restoration). It achieves 10.5% average DRAM energy reduction and 7.3% system energy savings with only 1.8% average performance loss across memory-intensive workloads, leveraging a performance model to balance energy and latency trade-offs in modern DDR3L chips.

ABSTRACT

This paper summarizes our work on experimental characterization and analysis of reduced-voltage operation in modern DRAM chips, which was published in SIGMETRICS 2017, and examines the work's significance and future potential. We take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the DRAM supply voltage is lowered below the nominal voltage level specified by DRAM standards. We perform an experimental study of 124 real DDR3L (low-voltage) DRAM chips manufactured recently by three major DRAM vendors. We find that reducing the supply voltage below a certain point introduces bit errors in the data, and we comprehensively characterize the behavior of these errors. We discover that these errors can be avoided by increasing the latency of three major DRAM operations (activation, restoration, and precharge). We perform detailed DRAM circuit simulations to validate and explain our experimental findings. We also characterize the various relationships between reduced supply voltage and error locations, stored data patterns, DRAM temperature, and data retention. Based on our observations, we propose a new DRAM energy reduction mechanism, called Voltron. The key idea of Voltron is to use a performance model to determine by how much we can reduce the supply voltage without introducing errors and without exceeding a user-specified threshold for performance loss. Our evaluations show that Voltron reduces the average DRAM and system energy consumption by 10.5% and 7.3%, respectively, while limiting the average system performance loss to only 1.8%, for a variety of memory-intensive quad-core workloads. We also show that Voltron significantly outperforms prior dynamic voltage and frequency scaling mechanisms for DRAM.

Motivation & Objective

• To understand the voltage-latency-reliability trade-offs in modern DRAM chips under reduced supply voltage.
• To characterize how voltage scaling affects DRAM reliability, latency, data retention, and error patterns.
• To design a low-cost, runtime mechanism that enables aggressive DRAM voltage scaling without sacrificing data integrity.
• To minimize system energy consumption while constraining performance loss within user-specified bounds.
• To enable new energy-efficient memory system designs by exposing exploitable trade-offs in DRAM operation.

Proposed method

• Built an FPGA-based testing platform using SoftMC to control DRAM supply voltage and adjust timing parameters.
• Conducted experimental characterization on 124 real DDR3L DRAM chips from three vendors across varying voltages, temperatures, and data patterns.
• Used SPICE circuit simulations to validate and explain experimental findings on voltage-latency-reliability relationships.
• Proposed Voltron, a mechanism that uses a piecewise linear performance model to determine optimal voltage scaling levels based on acceptable performance loss.
• Applied voltage scaling selectively to the DRAM array while maintaining nominal voltage for peripheral circuits to sustain high memory channel frequency.
• Dynamically increased latency of activation, precharge, and restoration operations to compensate for reduced voltage and eliminate bit errors.

Experimental results

Research questions

• RQ1 How does reducing DRAM supply voltage below nominal levels affect reliability, latency, and data retention in modern DDR3L chips?
• RQ2 What is the relationship between reduced voltage and the location and pattern of bit errors in DRAM data?
• RQ3 Can increasing the latency of fundamental DRAM operations (activation, precharge, restoration) eliminate errors caused by voltage scaling?
• RQ4 What is the optimal trade-off between voltage scaling, performance loss, and energy savings in DRAM systems?
• RQ5 How can a runtime mechanism exploit voltage-latency-reliability trade-offs to reduce energy without compromising reliability?

Key findings

• Reducing supply voltage below 1.35V induces bit errors in DRAM data, with error rates increasing as voltage decreases.
• Increasing the latency of activation, precharge, and restoration operations eliminates voltage-induced bit errors, enabling safe voltage scaling.
• The relationship between voltage, error location, and data pattern is non-uniform and dependent on chip-specific process variations.
• Voltron reduces average DRAM energy consumption by 10.5% and system energy by 7.3% across a range of memory-intensive workloads.
• Voltron achieves these savings with only a 1.8% average performance loss, significantly outperforming prior dynamic voltage and frequency scaling techniques for DRAM.
• The experimental characterization reveals that voltage scaling can be safely exploited across a wide range of supply voltages, enabling new energy optimization opportunities in memory systems.