[Paper Review] An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

Behzad Salami, Erhan Baturay Onural+7 more|arXiv (Cornell University)|May 4, 2020

Advanced Memory and Neural ComputingEngineering144 references49 citations

TL;DR

The paper experimentally analyzes undervolting in modern FPGAs for CNN inference, quantifies the voltage guardband, and shows over 3x power-efficiency gains with controlled accuracy loss, aided by frequency scaling, quantization, and pruning.

ABSTRACT

We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect of environmental temperature on the reliability-power trade-off of such accelerators. We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.

Motivation & Objective

• Characterize the power and reliability impact of reduced-voltage operation on FPGA-based CNN accelerators.
• Determine the size of the FPGA voltage guardband and the reliability/accuracy implications of undervolting below it.
• Evaluate techniques (frequency underscaling, quantization, pruning) to mitigate accuracy loss while maintaining power-efficiency.
• Assess environmental temperature effects on power-reliability trade-offs in undervolted FPGA CNN accelerators.
• Study hardware variability by testing multiple identical FPGA platforms to understand guardband and crash voltage variations.

Proposed method

• Experimentally undervolt VCCINT on three identical Xilinx ZCU102 FPGA boards using PMBus-controlled voltage rails.
• Map five CNN benchmarks (VGGNet, GoogleNet, AlexNet, ResNet50, Inception) to DPUs on FPGA and measure power, accuracy, and throughput.
• Identify voltage regions: guardband (no accuracy loss), minimum safe voltage V_min (no accuracy loss but reduced margin), critical region (accuracy loss begins), V_crash (system non-functional).
• Apply frequency underscaling to compensate accuracy loss in the critical region and evaluate energy-efficiency metrics (GOPs, GOPs/W, GOPs/J).
• Combine undervolting with CNN quantization (INT8–INT4 tested) and pruning to study trade-offs between accuracy and power-efficiency.
• Examine environmental temperature effects by varying ambient temperature and measuring impact on power and reliability.

Experimental results

Research questions

• RQ1 What is the average voltage guardband below nominal V_nom for VCCINT on modern FPGA platforms?
• RQ2 How does undervolting below the guardband affect CNN accuracy and overall power-efficiency across standard CNN models?
• RQ3 Can frequency underscaling or architectural techniques (quantization/pruning) mitigate accuracy loss while maintaining or improving power-efficiency?
• RQ4 How does environmental temperature influence the power-reliability trade-off under reduced-voltage operation?
• RQ5 What is the degree of hardware platform variability in guardband and crash voltages across identical FPGA boards?

Key findings

• Average voltage guardband for VCCINT is about 280 mV (V_min ≈ 570 mV with V_nom = 850 mV).
• Minimum safe voltage V_min is 570 mV on average; below this, accuracy remains stable until entering the critical region.
• Beyond V_min, undervolting yields power-efficiency gains up to >3x (GOPs/W) with increasing accuracy loss; 2.6x of this gain comes from removing the guardband, and an extra 43% from further undervolting in the critical region.
• V_crash occurs around 540 mV on average, where the FPGA becomes non-functional; workloads with more parameters (e.g., ResNet, Inception) are more vulnerable.
• Frequency underscaling can help mitigate accuracy loss in the critical region; however, the energy-optimal point tends to be the highest safe frequency at the lowest safe voltage (V_min).
• Quantization and pruning amplify power-efficiency gains under undervolting but slightly increase vulnerability to faults; pruned models show higher V_crash (555 mV) than baseline (540 mV).
• Environmental temperature affects power consumption and fault likelihood; at very low voltages, temperature effects are less noticeable.
• Internal FPGA components, especially on-chip BRAM/DPU resources, dominate power consumption; undervolting mainly targets VCCINT to reduce this load.