Byungsub Kim
Pohang University of Science and Technology · Engineering
About the Lab
Professor Byungsub Kim's research lab specializes in high-speed, energy-efficient on-chip and inter-chip interconnects, focusing on advanced equalization techniques and low-power transceiver architectures for next-generation integrated circuits. The lab develops innovative analog and mixed-signal circuits—such as charge-injecting transmitters, DFE-IIR receivers, and nonlinear pre-emphasis schemes—to overcome signal integrity challenges in high-loss, dispersive channels like on-chip wires and silicon carriers. Their work emphasizes design-space exploration, cross-layer modeling, and architectural optimization to achieve high throughput, low energy-per-bit, and compact area, targeting applications in multi-core processors and high-bandwidth packaging. The lab also explores control-theoretic methods to enhance system performance, particularly in repetitive signal control for precision applications.
Research Overview
Research Output Trend
Figures are computed from collected data and may differ slightly.
Selected Papers
15A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR). The DFE-IIR receiver uses a single additional IIR filter feedback tap to compensate many post cursors without paying the power and area penalty that would be incurred with a conventional
This work describes the architecture and circuit implementation of a high-data-rate, energy-efficient equalized transceiver for high-loss dispersive channels, such as RC-limited on-chip interconnects or silicon-carrier packaging modules. The charge-injection transmitter directly conducts pre-emphasis current from the supply into the channel, eliminating the power overhead of analog current subtraction in conventional transmit pre-emphasis, while significantly relaxing the driver coefficient accu
This paper presents a transceiver for fast and energy-efficient global on-chip communication, consisting of a nonlinear charge-injecting (CI) 3-tap transmit filter (TX) and a sampling receiver (RX) with transimpedance pre-amplifier (TIA). Recently, pre-emphasis techniques have demonstrated significantly better energy-efficiency than repeater interconnects. To further improve energy-efficiency over pre-emphasis techniques that require analog subtraction, our TX selects a pattern-dependent current
Abstract—This paper presents a modeling framework for fast design space exploration and optimization of equalized on-chip interconnects. The exploration is enabled by cross-layer modeling that connects the transistor and wire parameters to link performance, equalization coefficients, and architecture-friendly metrics (delay, energy-per-bit, and throughput density). Appropriate models are derived to speed-up the search by more than two orders of magnitude and make a million point design space sea
As the number of cores increases and onand off-chip bandwidth demand rises, it is becoming increasingly more difficult to rely on conventional interconnects and remain within the chip power budget. This article explores leveraging equalization for global and semi-global long interconnects to overcome this problem.
Bearing stiffness directly affects the dynamic characteristics in a high-speed spindle system and plays an important role in terms of manufacturing quality. We developed a new approach for predicting the thermal behavior of a high-speed spindle, calculated the thermal expansion, and generated a bearing stiffness matrix for angular contact ball bearings. The heat convection of spindle housing in air, the balls in lubricant, the spindle shaft in quiescent air, and the bearing inner ring surfaces w
This paper presents a method for enhancing the performance of a digital repetitive control system. The performance at the fundamental frequency and its harmonics of repetitive exogenous signals is improved by applying a modified low-pass qz,z−1 filter structure in the repetitive signal generator of the internal model. Stability and robust performance is achieved through μ-synthesis. The modified low-pass filter is motivated by the attempt to reduce the sensitivity function by squaring it. The ma
Presents the design of a digital repetitive controller with improved performance via a discrete-time /spl mu/-synthesis technique. The performance improvement at the fundamental frequencies is obtained by a modified lowpass q(z, z/sup -1/) filter structure and robust stability is obtained through p-synthesis design methodology. The new structure of the q(z, z/sup -1/) filter is motivated by efforts to square the sensitivity function which has very small values at the fundamental frequencies. The
This paper presents a robust repetitive controller design for a dual stage actuator system for the noncircular cam turning process. The secondary actuator in this dual stage system is a piezoelectric actuator which is installed inside of the hollow piston of an electrohydraulic actuator. The controller is designed through a sequence of two SISO designs under the assumption that there is little interaction between two actuator systems. The error from the first stage electrohydraulic actuator is f
This paper addresses the tracking of near periodic time vary-ing signals by proposing an integrated approach for simultane-ously designing previewed feedforward, feedback, and repetitive control in a unified framework. The design problem is formu-lated as a µ-synthesis problem, in which the distance between a specified reference model and the achievable tracking perfor-mance with feedforward compensation is minimized in terms of the structure singular value. Desired upper bounds of disturbance r
Research Areas
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