Dongyun Kam

Graph convolutional neural networks (GCNs) have emerged as a key technology in various application domains where the input data is relational. A unique property of GCNs is that its two primary execution stages, aggregation and combination, exhibit drastically different dataflows. Consequently, prior GCN accelerators tackle this research space by casting the aggregation and combination stages as a series of sparse-dense matrix multiplication. However, prior work frequently suffers from inefficien

Allowing the superior error-correction performance even for short-length codewords, the successive-cancellation list (SCL) decoding algorithm has allowed the polar code to be adopted in 5G New Radio standard for control channel. However, existing SCL polar decoders still suffer from long processing latency caused by a number of serialized internal operations. In this work, to solve the latency problem, we present several parallel computing solutions for the serialized operations, i.e., simplifie

This paper presents a cost-efficient large-list SCL polar decoder supporting an ultra-reliable channel coding in 5G and beyond communications. To minimize huge implementation costs, the proposed design utilizes fully-reusable LLR buffers associated with stage unfolding and LLR overwriting schemes, significantly reducing the on-chip buffer overheads by 67% compared to the state-of-the-art decoder. Implemented in a 28nm CMOS, the prototype list-8 decoder achieves 1.1μs and 1.56Gb/s/mm <sup xmlns:m

In massive multiple-input multiple-output (MIMO) systems using a large number of antennas, it would be difficult to connect high-resolution analog-to-digital converters (ADCs) to each antenna component due to high cost and energy consumption problems. To resolve these issues, there has been much work on implementing symbol detectors and channel estimators using low-resolution ADCs for massive MIMO systems. Although it is intuitively true that using low-resolution ADCs makes it possible to save a

To enable emerging mission-critical applications, e.g., healthcare monitoring, remote surgery, and autonomous driving, 5G/6G ultra-reliable low-latency communication (URLLC) devices demand the concurrent fulfillment of ultra-reliability, low-latency, and low-power communications, particularly in short data transmissions as depicted in Fig. 2.8.1. However, the existing short-length forward error-correction (FEC) solutions for URLLC devices cannot meet all the challenging requirements at the same

The ordered statistic decoding (OSD) approach for short-length BCH codes has been continuously considered as one of the promising error-correction codes by achieving a block error rate (BLER) of less than $10^{-6}$, which is attractive to the ultra-reliable and low-latency communication (URLLC) for industrial IoT (IIOT) solutions [1], [2]. However, it is hard to directly realize the conventional OSD algorithm because of the compute-intensive Gaussian elimination and iterative reprocessing steps.

In this paper, we present a novel scheduling method that reduces the latency of polar decoders significantly. Unlike the prior pruning-based successive cancellation list (SCL) decoding that suffers from a number of idle cycles, the proposed overlapped SCL scheme immediately begins node operations without waiting for the list to be sorted, being exempt from such unfavorable cycles. All possible candidates for the next node operations are precomputed in parallel with the pruning operations, and ar

In this paper, we introduce the design and veri-fication frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes. We also present a hardware-level framework to rapidly evaluate the performance of a ternary processor implemented in arbitrary design technology. As a

Due to an iterative nature, a low-density parity-check (LDPC) decoder is associated with a long latency, being a major bottleneck of the baseband processor in wireless communication systems. Based on the practical min-sum (MS) decoding method, in this paper, we present a cost-effective algorithm for reducing the processing latency of LDPC decoders. By checking the number of short-length cycles in the LDPC code structure, the proposed method dynamically changes the reweighting factor at the itera

Achieving the attractive error-correcting capability with a simple decoder structure, the polar code using successive cancellation (SC) decoding is now expected to be installed at the resource-limited IoT or embedded communications. However, the existing SC decoders normally suffer from the long processing latency caused by the serialized processing steps, limiting the practical applications of polar codes. In this article, to solve this latency problem, we present a new low-complexity merging o

The emerging digital audio compression technology brings both an opportunity and a new challenge to IC design. High quality multichannel audio is quickly becoming an indispensable part of an entertainment system. The algorithms used in the compression technology result in complex VLSI ICs. The work presented in this paper is about the design of a dedicated, high precision, and low cost AC3/MPEG multi-standard audio decoder. The audio IC's hardware and software architecture, as well as design and

In this paper, we newly present a novel parallel polar decoding architecture that significantly reduces the processing latency for 5G wireless communications. Based on the original decoding tree, the proposed scheme first constructs the small trees that generate multiple soft-decision messages in parallel, potentially reducing the decoding latency compared to the previous serialized schemes. The hard-decision estimates are then calculated at the following merging step to decide the decoded outpu

This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the ne

The sorting operation plays a vital role in various signal processing applications. However, due to high hardware complexity resulting from a series of comparisons, designing the cost-efficient sorter is one of the crucial requisites for improving the overall system performance. To obtain the cost-efficient sorting architectures constrained to application-specific input/output conditions, this paper presents a systematic design methodology that effectively eliminates dispensable compare-and-swap

Low bit-precisions and their bit-slice sparsity have recently been studied to accelerate general matrix-multiplications (GEMM) during large-scale deep neural network (DNN) inferences. While the conventional symmetric quantization facilitates low-resolution processing with bit-slice sparsity for both weight and activation, its accuracy loss caused by the activation’s asymmetric distributions cannot be acceptable, especially for largescale DNNs. In efforts to mitigate this accuracy loss, recent st