Edward Choi

In this letter, we present a multi-bit SRAM computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNN). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient “one-step" method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multi-bit weight with bit-shifting in the charge domain

Over the years, SRAM-based compute-in-memory (CIM) structures have shown ways to perform deep neural network (DNN) computations in the mixed-signal domain with high energy efficiency but suffer from the tradeoff and limitations in their accuracy arising from analog nonidealities. Recently, circuit techniques were developed to support multi-bit analog computations in SRAM-based CIM macro [1], [2], which computes multiplication and accumulation by using transistor currents. However, the transistor

Computing-in-memory (CIM) has been an ongoing prominent research area for easing the energy efficiency of machine learning tasks in edge devices. Recently, embedded non-volatile memory (eNVM) CIM architectures have been popular as an edge device, where it can turn off their supply during standby for low power consumption. However, most eNVMs (e.g., MRAMs and RRAMs) require the use of specialized technologies and are mostly used as single-level cell (SLC) data storage [2], [3]. In the technologie

This work presents a 4 kb 8T-SRAM computation-in-memory (CIM) macro based on hybrid computation using digital in-memory-array computing (DIMAC) and phase-domain near-memory-array computing (PNMAC). By employing multiple local dual-column arrays (LDCAs), bit-wise multiplications are computed digitally in memory with high energy efficiency and throughput. The PNMAC performs the summation and accumulation in parallel with a high dynamic range by using a proposed steering-DAC-based differential curr

In analog-mixed-signal (AMS) compute-in-memory (CIM) systems, the two’s-complement (2SC) format provides better area efficiency than the sign-and-magnitude (SNM) one. However, the 2SC format exacerbates the challenges of AMS-CIM systems, suffering from significant DNN accuracy drop under process variations and high computation currents from activating multiple WLs. In the 2SC format, ‘0’ and ‘1’ are nearly balanced for all logical-order bits, unlike ‘0’-skewed higher-order bits in the SNM format

The proposed <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta$</tex>-based spike sorting (SS) SoC is the first on-chip implementation of an analog computing-in-memory (CIM) binary autoencoder neural network (B-AENN) feature extraction with enhanced spike detection adopting <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta$</tex>-spikes, resulting in the highest on-chip SS classification acc

This work presents an SRAM-based analog reconfigurable computing-in-memory macro with 409.6-GOPS throughput and 460.22-TOPS/W energy efficiency. The proposed reconfigurable macro supports $1 / 2 / 4 / 8 \mathrm{~b}$ inputs and $1 / 2 / 4 / 8 \mathrm{~b}$ signed weights while maintaining 100% memory utilization. Furthermore, we propose (i) a dual-domain DAC to achieve high-precision input with low area overhead and (ii) an input-sense-and-skip SAR ADC, which reduces the average power overhead by

BACKGROUND: Posttransplant opioid dependence has been linked to adverse outcomes in solid organ transplantation, but its impact on pancreas transplantation is underexplored. METHODS: This retrospective study analyzed 193 PTA/PAK recipients from Asan Medical Center (AMC) (2010-2022) and externally validated results in 77 recipients from Pusan National University Yangsan Hospital (PNUYH) (2015-2022). Posttransplant opioid dependence was defined as ≥ 10 opioid prescriptions between 3 and 12 months

The LLM-based approach provides a practical and scalable solution for expanding radiology ontologies while maintaining semantic alignment; the method can aid real-world natural language processing applications.

The proposed multi-seizure-type classifier (MSTC) SoC is the first on-chip classification of multiple seizure types, integrating frequency-based feature fusion (FF) and digital ternary near memory computing (NMC) to achieve a classification accuracy of 91.63 % with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$24.72 \mu ~\mathrm{s}$</tex> computational latency. The MSTC SoC is also the first true zero-shot seizure detection system requiring no pa

This is an exploratory study that discovers the current image quantization (vector quantization) do not satisfy translation equivariance in the quantized space due to aliasing. Instead of focusing on anti-aliasing, we propose a simple yet effective way to achieve translation-equivariant image quantization by enforcing orthogonality among the codebook embeddings. To explore the advantages of translation-equivariant image quantization, we conduct three proof-of-concept experiments with a carefully

This paper presents an SRAM-based input bit configurable pulse-train computing-in-memory (CIM) macro for edge devices. The proposed macro computes matrix-vector-multiplications (MVM) in a bit-wise manner, generating pulse trains to overcome the limited signal margin and variations occurring in analog time-domain SRAM-based CIM macros. Furthermore, the system architecture comprises an error-free dynamic OR gate discharge computation, effectively addressing the non-linearity associated with analog

Radiology reports convey detailed clinical observations and capture diagnostic reasoning that evolves over time. However, existing evaluation methods are limited to single-report settings and rely on coarse metrics that fail to capture fine-grained clinical semantics and temporal dependencies. We introduce **LUNGUAGE** , a benchmark dataset of structured radiology reports that serves as a gold standard for evaluating structured report frameworks. It is designed to support comprehensive assessmen

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To process the substantial data generated from on-chip neural recordings, a robust spike sorting (SS) system-on-chip (SoC) with minimal latency is essential to ensure timely response in closed-loop brain–computer interface (BCI) applications. In this article, we report a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $</tex-math> </inline-formula>-based SS SoC featuring the first on-chip incorporation