Heon-Joon Lee

OBJECTIVES: The current study was performed to (1) understand the distribution of airborne fungi culturable on dichloran-glycerol agar (DG18) media over a one-year monitoring period, (2) identify the types of airborne fungi collected, and (3) compare and contrast under- and above-ground spaces, in two railway stations in Tokyo, Japan. METHODS: Measurements of airborne fungi were taken at stations A and B located in Tokyo. Station A had under- and above-ground concourses and platforms whereas sta

The crossbar structure of the nonvolatile memory enables highly parallel and energy-efficient analog matrix-vector-multiply (MVM) operations. To exploit its efficiency, existing works design a mixed-signal deep neural network (DNN) accelerator, which offloads low-precision MVM operations to the memory array. However, they fail to accurately and efficiently support the low-precision networks due to their naive ADC designs. In addition, they cannot be applied to the latest technology nodes due to

To understand how the human brain works, neuroscientists heavily rely on brain simulations which incorporate the concept of time to their operating model. In the simulations, neurons transmit their signals through synapses whose weights change over time and by the activity of the associated neurons. Such changes in synaptic weights, known as learning, are thought to contribute to memory, and various learning rules exist to model different behaviors of the human brain. Due to the diverse neurons

The modern x86 processor (e.g., Intel, AMD) translates CISC-style x86 instructions to RISC-style micro operations (uops) as RISC pipelines are more efficient than CISC pipelines. However, this x86 decoding process requires complex hardware logic (i.e., x86 decoder) to identify variable-length x86 instructions, which incurs high translation overhead. To avoid this overhead, the x86 processors adopt a micro-operation cache (uop cache) to bypass the expensive x86 decoder by caching the decoded uops

Brain-inspired computing aims to understand the cognitive mechanisms of a brain and apply them to advance various areas in computer science. Deep learning is an example to greatly improve the field of pattern recognition and classification by utilizing an artificial neural network (ANN). To exploit advanced mechanisms of a brain and thus make more great advances, researchers need a methodology that can simulate neural networks with higher computational capabilities such as advanced spiking neura

OBJECTIVES: We performed the current study to (1) understand the distribution of culturable airborne bacteria over a one-year monitoring period, (2) confirm places in stations where airborne bacteria are highly detected, (3) understand the factors that affect concentrations of airborne bacteria and (4) compare the distributions of airborne bacteria and fungi in railway stations in Japan. METHODS: Measurements of airborne bacteria were taken at stations A and B located in Tokyo. Station A had und

To understand and mimic the working mechanism of the brain, neuroscientists rely on brain simulations that operate in a time-driven manner. The simulation involves evaluating how the neurons change their states over time and transferring spikes to the connected neurons through synapses. It also simulates learning by evaluating how the synapses change their weights according to the spiking activity of the neurons. To explore various behaviors of the brain and thus make great advances, neuroscient

住環境には数多くの真菌が分布しており,これら真菌がアレルゲンとして重視されつつある.筆者らは,生活環境中にみる真菌の生態分布について,さまざまな角度から検討してきた.ここでは,生活環境と真菌との関わりで重要な空中(屋内,屋外),ハウスダスト,空調機フィルター,室内真菌汚染環境に焦点をあて,それぞれの因子にみる主要真菌をまとめた.共通して分布する真菌として,Cladosporium, Penicillium, Aspergillusがあり,これら真菌以外での分布は,各環境,基質に強く依存することから,住環境中での真菌分布を作成し,アレルゲンとしての真菌を紹介した.

Brain-computer interfaces (BCIs) are electrophysiological devices (e.g., electrode arrays) that connect the brain to a computer. They offer neuroscientific and neurological innovations by utilizing a dedicated processor for continuous BCI signal processing. Recent studies propose a scaled-up BCI that adopts an order of magnitude larger number of electrodes to more precisely interface with the brain. As the BCI scales, utilizing a spike-driven processor emerges as an alternative processing method

Nowadays, as the demand for accurate object detection (OD) applications is increasing, several attempts have been made to introduce convolutional neural network (CNN)-based super-resolution (SR) into these applications to further improve their target accuracy. OD systems require real-time processing because they are widely used in latency-critical applications such as autonomous driving, augmented reality, and surveillance cameras. However, due to their high computational and memory requirements

Brain-computer interfaces (BCIs) provide an interactive closed-loop connection between the brain and a computer.By employing signal processors implanted within the brain, BCIs are driving innovations across various fields in neuroscience and medicine.Recent studies highlight the need to integrate non-volatile memories (NVMs) into the implanted system for large-scale applications.At the same time, they emphasize the importance of continual learning within the system to address non-stationarities

Brain-computer interfaces (BCIs) have made remarkable progress in recent years, driven by advances in neuroscience and clinical applications. For practical use, underlying processing systems must meet strict latency and power budgets. However, existing BCI systems typically rely on a single processing node to handle the entire workload, making it difficult to satisfy these budgets across diverse applications. In this work, we present TierX, the first simulation framework for design space explora

Analog Computing-in-Memory (ACiM) devices perform matrix operations directly within memory arrays, offering high throughput for deep neural network inference. At the same time, they are susceptible to various noise sources, which reduces the computational accuracy. This inherent trade-off limits the adoption of ACiM devices as a stand-alone accelerator. In this paper, we propose the first heterogeneous inference-serving framework that coordinates ACiM hardware and conventional digital processors

With the widespread adoption of Deep Neural Networks (DNNs), Neural Processing Units (NPUs) are emerging as energy-efficient alternatives to GPUs through parallel processing and high data reuse. However, since diverse deep learning kernels have different memory and computation resource requirements, a utilization imbalance between memory and computation resources often occurs.