Hoyong Choi

Purpose The purpose of this paper is to present a fully integrated power converter. A stacked spiral inductor is applied in a voltage‐mode CMOS DC‐DC converter for the chip miniaturization and low‐power operation. Design/methodology/approach The three‐layer spiral inductor is simulated with an equivalent circuit and applied to the DC‐DC converter. The DC‐DC buck converter has been fabricated with a standard 0.35 μ m CMOS process. The power converter is measured in both experiment and simulation

Many recent works on understanding deep learning try to quantify how much individual data instances influence the optimization and generalization of a model. Such attempts reveal characteristics and importance of individual instances, which may provide useful information in diagnosing and improving deep learning. However, most of the existing works on data valuation require actual training of a model, which often demands high-computational cost. In this paper, we provide a training-free data val

This paper presents a dual-mode DC-DC buck converter using power transistor width scaling (PTWS) with a zero current detector to improve power efficiency under light load. The buck converter is operated in a dual mode, combining the switching frequency modulation (SFM) mode which uses the voltage controlled oscillator (VCO) under light load, with the PWM mode for heavy load. To enhance power efficiency under light load a PTWS scheme is employed, in which the inductor current is detected using a

This paper proposes a charge pump that minimizes the current mismatch and keeps the constant current across a wide range of output voltage. The charge pump is a two-stage circuit which is composed of the conventional push-pull charge pump and the compensation circuit. The compensation circuit has a feedback biasing circuit and an op-amp to act as a voltage follower. The features of feedback circuit and voltage follower are the important elements to reduce the current mismatch. The proposed charg

Purpose – The paper aims to design of dual-mode boost converter with integrated low-voltage control circuit is introduced in this paper. The paper aims to discuss these issues. Design/methodology/approach – The converter is operated either with LC filter or with charge pump circuit by the switch control. The control stage with error amplifier, comparator, and oscillator is designed with the supply voltage of 3.3 V and the operating frequency of 5.5 MHz. The compensator circuit exploits a pole co

Abstract We investigate the primary and secondary market reactions of US corporate bonds to the mandatory Environmental, Social, and Governance (ESG) Disclosure Act of 2021 (hereafter, the ESG Disclosure Act). We compare ESG bonds with non‐ESG bonds through a yield spread analysis for the primary market and a bond event study for the secondary market, assessing the impact on a sustainable premium (“sustainium”) following the enactment. Sustainium disappears from the primary market after the ESG

Purpose The purpose of this paper is to introduce a low power digital‐to‐analog converter (DAC) by using a sequential triggering technique in cascaded current source. Design/methodology/approach The block of current cell consists of current switch and source. A sequential switching on process is implemented with the current triggering technique in source. An experiment of 12‐b 150‐MS/s DAC has been integrated in a single‐poly four‐metal 0.35 μm CMOS process. Findings Compared with conventional c

Purpose – This paper aims to design the circuit for electromagnetic interface (EMI) reduction in liquid crystal display (LCD). Design/methodology/approach – The cascode level shifter and segmented driver circuit are applied in LCD column driver integrated circuit (IC) for EMI reduction. Cascode current mirror is used in the proposed level shifter for DC voltage biasing and reduction of the driving current which passes through the level shifter. The on-off switching currents and transient times a

In this paper, we propose a distributed TDMA MAC protocol over wireless ad-hoc networks, called CH-MAC. The key design component of CH-MAC is the notion of clusters, where a cluster head maintains the information about how slots are allocated over the one-hop neighborhood. This cluster-based operation enables CH-MAC to opportunistically operate in a hybrid fashion of being both reactive and proactive. In other words, once a node intends to be allocated some slots, its cluster head provides the i

In this paper, we propose a design of a two-channel high-performance DC-DC converter that provides a positive voltage VPOS with a low ripple, and a negative voltage VNEG with high power efficiency, for the purpose of enhancing power efficiency and output ripple under light loads of 100 mA or less for mobile active-matrix organic light-emitting diode (AMOLED) displays. The VPOS was designed as a boost converter using a novel input voltage variation reduction circuit (IVVRC), which rapidly changes

This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35µm CMOS process. The simulat

In this paper, an integrated low-voltage control circuit is introduced for a charge pump DC-DC boost converter. By exploiting the advantage of the integration of the feedback control circuit within CMOS technology, the charge pump boost converter offers a low-current operation with small ripple voltage. The error amplifier, comparator, and oscillator in the control circuit are designed with the supply voltage of 3.3 V and the operating frequency of 1.6~5.5 MHz. The charge pump converter with the

Feedback control for self-triggering frequency modulation is proposed for an integrated buck-boost DC-DC converter in an AMOLED display. The goal is to reduce the ripple noise and transient time during the switching process. The converter uses two control modes: switching frequency modulation (SFM) mode for light load current and pulse width modulation (PWM) mode for heavy load current, which result in high power efficiency over a wide range of load current. The mode is automatically changed acc

This paper introduces a low power frequency divider in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. Ring oscillator operates at 1 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). The structure of ILFD is designed to be similar with that of oscillator in order to adjust the frequency alignment between the oscillator