Hyung Joon Kim

In this paper, efficiency-limiting physical constraint effects imposed on the knee voltage, along with a variation of the optimum load resistance, are investigated for highly efficient Class-F and Class- amplifiers. First, for an accurate analysis and comparison, new current waveform models are identified, and a realistic approach incorporated using a nonzero knee voltage and voltage-dependent nonlinear capacitance is employed to derive the voltage waveforms of the amplifiers. An analysis is per

In this paper, an analysis of a power amplifier manipulated using a second harmonic (PA-2HM) is described using a remarkable correlation between the fundamental and second harmonic impedances. The output loading condition, made up of an optimum fundamental impedance mapped to the conditional second harmonic reactance, allows us to achieve a high-efficiency power amplifier (PA) with a simple output matching circuit. For the analysis, the output voltage and current waveforms are modeled in terms o

We demonstrate a new linearized monolithic microwave integrated circuit smart power amplifier of extraordinary high power-added efficiency (PAE), especially at the most probable transmission power of wide-band code-division multiple-access handsets. A PAE of 21% at 16 dBm of output power, which is the maximum bound of the most probable transmission power in IS-95 systems, was obtained, as well as 40% at 28 dBm, the required maximum output power, with a single-chip MMIC power amplifier. The power

This brief proposes a wideband CMOS power amplifier (PA) with flat gain using a pole-controlled transformer in the sub-THz band for wireless chip-to-chip communication. An analysis of the transformer-based interstage matching network is presented, which indicates a zero in-band ripple condition. For verification, a pole-controlled PA (with an area of 0.33 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{{2

This paper presents a 120 GHz low-power wideband I/Q transmitter in a 40 nm CMOS technology for wireless chip to chip communication. The proposed transmitter consists of an up-conversion mixer, a Quadrature Injection-Locked Oscillator (QILO), gain amplifiers, and a power amplifier. The cross-coupled-capacitor topology was used to improve the conversion gain of the up-conversion mixer. By adopting a Iinearizer, the power amplifier achieved an output P1dB of 11 dBm. The transmitter exhibited a con

In this paper, a new envelope amplifier (EA) scheme incorporating a linear regulator array is presented. The proposed EA achieves a higher efficiency over a wide envelope range utilizing multiple linear regulators. The linear regulators biased as multiple supply voltages are responsible for delivering a partial envelope current, ensuring high efficiency. A simulation revealed the superior performance efficiency of the proposed scheme in terms of the instantaneous envelope voltage compared with t

This paper presents a new power amplifier architecture incorporating a multi-level envelope delta sigma modulation (EDSM) encoder together with a dynamic bias control method to improve the overall efficiency. The proposed transmitter was developed based on a 3-level encoding process for quantizing the non-constant envelope signal. Therefore, the power amplifier is always operated under only a two-state output power level (maximum and 6dB back-off levels), achieving high efficiency. To maintain t

In this paper, a high-efficiency envelope-tracking (ET) transmitter incorporating a novel efficiency-boosting function is proposed and implemented. An inverse Class-F power amplifier is utilized and optimized using the proposed output loading condition, which enhances its efficiency at the high probability region. This matching network can be conveniently implemented by controlling the nonlinear capacitance of the power transistor. For an accurate analysis, the output waveforms are modeled in te

In this letter, an efficiency enhancement technique incorporating a gate-voltage boosting of a peaking power amplifier (PA) in a CMOS Doherty PA is presented. To compensate the current driving capability from the low dc bias point of the peaking cell, an auxiliary bias network consisting of an operational amplifier (OPA) is utilized to provide the corresponding gate voltage in accordance with an instantaneous output power level. To verify the superior performance of the proposed technique, a CMO

An amplitude-phase (AM-PM) linearization technique using a direct drain-gate feedback method in a cascode CMOS amplifier is proposed. This technique consists of a series-connected capacitor and an inductor coupling the residue of the RF signal drain. The coupled RF ac signal to gate node of the common gate stage (CG) prevents the CG stage from entering the triode region at a high output power region. In this respect, the parasitic gate-drain capacitance sustains a constant value, achieving an en

This paper presents a 1.5 bit (3-level) envelope amplifier to improve the overall efficiency of wideband high linearity envelope tracking power amplifier. The proposed envelope amplifier has been devised with two switches providing the different supply voltages. Since the unnecessary current (ripple current) induced by a switching stage can be reduced by the multi-level quantization, the efficiency of a proposed envelope amplifier is 5% higher compared with that of a conventional architecture. W

In this paper, the effect of the fundamental current provided by a peaking cell consisting of a Doherty amplifier is analyzed using a new closed-current model. The proposed current model can be used as a foundation to accurately explain and optimize previous compensation methods such as uneven, asymmetric, and gate envelope cases. Based on the proposed analysis, and in conjunction with the envelope tracking scheme, two-point envelope modulation simultaneously supplying the carrier and peaking ce

A new type of source matching for improving the efficiency of an inverse Class-F (Class-F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) amplifier is presented. The squared waveform voltage is generated by adjusting the phase of finite second harmonic voltage shift. To verify the superior performance of the proposed technique, two-stage HBT PAs with different types of source matching were fabricated using a commercial process. The propos

A new signal processing method that partially encodes the envelope signal using a delta sigma modulator (EDSM) into a bi-level signal according to the magnitude of the envelope, has been introduced to utilize a high efficiency class-C amplifier for linear amplification. The RF signal is synthesized through the proposed envelope waveform, which is encoded into a pulse signal in the lower power region and bypassed in power regions higher than the base threshold. In this respect, the magnitude of t