Hyungjin Kim

The superior density of passive analog-grade memristive crossbar circuits enables storing large neural network models directly on specialized neuromorphic chips to avoid costly off-chip communication. To ensure efficient use of such circuits in neuromorphic systems, memristor variations must be substantially lower than those of active memory devices. Here we report a 64 × 64 passive crossbar circuit with ~99% functional nonvolatile metal-oxide memristors. The fabrication technology is based on a

Although arithmetic coding offers extremely high coding efficiency, it provides little or no security as traditionally implemented. We present a modified scheme that offers both encryption and compression. The system utilizes an arithmetic coder in which the overall length within the range [0,1) allocated to each symbol is preserved, but the traditional assumption that a single contiguous interval is used for each symbol is removed. Additionally, a series of permutations are applied at the input

We demonstrate the hardware implementation of spiking neural network (SNN) with synaptic transistors and neuron circuits. The method of conversion from software fully-connected network (FCN) to hardware SNN with little degradation is discussed. The degradation of classification accuracy is analyzed in terms of device variation and noisy images. In addition, the accuracy degradation is significantly improved by stacking denoising autoencoder (DAE) layer. FCN-SNN conversion with very little perfor

A new synaptic transistor was fabricated with two separated gates based on a FinFET structure in order to mimic short- and long-term memories in a biological synapse and connect with a postsynaptic neuron circuit directly. The transition between short- and long-term memories occurred after applying repetitive input pulses and strongly depended upon intervals between input pulses. These findings indicate that it has very similar learning characteristics with a biological synapse and the possibili

In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper,

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of

To apply resistive random‐access memory (RRAM) to the neuromorphic system and improve performance, each cell in the array should be able to operate independently by reducing device variation. In addition, it is necessary to lower the operating current of the RRAM cell and enable gradual switching characteristics to mimic the low‐energy operations of biological. In most filamentary RRAMs, however, overshoot current occurs in the forming stage, and the RRAM shows large device variation, high opera

A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector-matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software

Although many studies have been continuously conducted to reduce the power consumption of a resistive random access memory (RRAM) cross-point array with the current-compliance effect, it has been difficult yet to realize intrinsic self-compliance effects in an RRAM device itself. In this study, a simple oxygen-rich TiOy layer is inserted into the Al2O3/TiOx-based RRAM stack as a current suppression layer, and XPS analysis is provided to compare the stoichiometry of the TiOx and TiOy layers. A se

We report the imaging findings in two patients with proliferating trichilemmal tumors. In the first patient, the tumor arose on the lower lip, a very unusual location for this type of tumor, and showed malignant transformation with metastasis to a regional lymph node. It was seen as a poorly marginated soft-tissue mass with isointense signal on T1-weighted MR images and hyperintense signal on T2-weighted images. Large areas of high signal intensity caused by necrosis were also found within the t

We propose a hardware-friendly architecture of a convolutional neural network using a 32 × 32 memristor crossbar array having an overshoot suppression layer. The gradual switching characteristics in both set and reset operations enable the implementation of a 3-bit multilevel operation in a whole array that can be utilized as 16 kernels. Moreover, a binary activation function mapped to the read voltage and ground is introduced to evaluate the result of training with a boundary of 0.5 and its est

In this work, a ZnO-based resistive switching memory device is characterized by using simplified electrical conduction models. The conventional bipolar resistive switching and complementary resistive switching modes are accomplished by tuning the bias voltage condition. The material and chemical information of the device stack including the interfacial layer of TiON is well confirmed by transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) analysis. The device exhibit

In this Letter, we present reset-voltage-dependent precise tuning operation of TiOx/Al2O3-based memristive devices. For the high resistance state (HRS) with high reset voltage, abrupt set operations are observed with a large variation, while the HRS obtained by low reset voltage provides gradual and uniform switching behaviors. The improvement of gradual switching and the programming accuracy are analyzed regarding cycle-to-cycle as well as device-to-device variations. We believe that these resu