Ic Park

As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the constant coefficient multiplications required in filters. The complexity of multiplier blocks can be significantly reduced by using an efficient number system. Although the canonical signed digit representation is commonly used as it guarantees the minimal number of additions for a constant multiplication, we propose in thi

In this paper, the authors propose an algorithm to find all the minimal signed digit (MSD) representations of a constant and present an algorithm to synthesize digital filters based on the MSD representation. The hardware complexity of a digital signal processing system is dependent on the number system used for the implementation. Although the canonical signed digit (CSD) representation is widely employed, as it is unique and guarantees the minimal number of nonzero digits for a constant, the M

A new heuristic scheduling algorithm which has a feature of escaping from local minima is presented. The algorithm has a polynomial time complexity in spite of its iterative nature. Although there is no guarantee for the optimality, the algorithm produced optimal results for the experimental examples of earlier works. A graph model which contains information on the real world constraints such as multi-cycle operations, chained operations and pipelined data paths is also proposed as a general mod

FAMOS, an iterative improvement scheduling algorithm for the high-level synthesis of digital systems, is described. The algorithm is based on a move acceptance strategy and various selection functions defined to represent the cost of hardware resources such as functional units and registers. A main feature of the algorithm is that it can escape from local minima. The algorithm can deal with diverse design styles such as multi-cycle operations, chained operations, pipelined datapaths, pipelined f

The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units (PUs) and complex interconnections. A practical solution of area-efficient decoders is to use the partially parallel architecture in which a PU is shared for several rows or columns. It is important in the partially parallel architecture to determine the rows or columns to be processed in a PU and their processing order. The d

Square and square-root are widely used in digital signal processing and digital communication algorithms, and their efficient realizations are commonly required to reduce the hardware complexity. In the implementation point of view, approximate realizations are often desired if they do not degrade performance significantly. In this paper, we propose new linear approximations for the square and square-root functions. The traditional linear approximations need multipliers to calculate slope offset

Square-related functions such as square, inverse square, square-root and inverse square-root operations are widely used in digital signal processing and digital communication algorithms, and their efficient realizations are commonly required to reduce the hardware complexity. In the implementation point of view, approximate realizations are often desired if they do not degrade performance significantly. In this paper, we propose new linear approximations for the square-related functions. The tra

Modeling and simulating pipelined processors in procedural languages such as C/C++ requires lots of cost in handling concurrent events, which hinders fast simulation. A number of researches on simulation have devised speed-up techniques to reduce the number of events. This paper presents a new simulation approach developed to enhance the simulation of pipelined processors. The proposed approach is based on early pipeline evaluation that all the intermediate values of an instruction are computed

To remove glitches occurring in NAND‐based digitally controlled delay lines (DCDLs), a novel glitch‐free architecture is presented. Compared with the previous structures requiring multiple control steps, the proposed DCDL employs a self‐delayed inner loop to remove all the glitches by applying a single‐step control‐code switching, reducing the control complexity remarkably without increasing the minimum delay as well as the resolution.

In the design of microprogrammed processors, the minimization of microcode width is very crucial to reduce the required microcode ROM area. The paper suggests two different procedures which are complementary in nature: first an integer linear programming formulation which guarantees an optimal solution for small or medium size problems; and second, a heuristic algorithm based on the graph bipartitioning to deal with large size problems. Experimental results show that the proposed heuristic algor

A simple yet effective method is proposed to reduce the hardware complexity of tree expansion in multiple‐input multiple‐output (MIMO) symbol detection. Tree‐expansion equations are transformed in the proposed method so as to maximise common subexpressions that can be shared. The proposed method reduces the number of operators significantly, especially multipliers which are costly, without any degradation of bit error rate.

A simple yet effective method is proposed to reduce the hardware complexity of min‐sum‐based low‐density parity‐check (LDPC) decoders. The proposed method finds the second minimum from the last four candidates of the first minimum, and can be implemented with only a few hardware components. In the case of 64 inputs, the proposed method reduces the comparators and 2‐to‐1 multiplexers by 48 and 64% compared to the conventional method that finds two exact minima.

In the successive cancellation list decoding of polar codes, the metric sorting dominates the overall decoding latency. To reduce the latency of metric sorting, this paper proposes a new sorting method, called interleaved local sorting, which divides the metrics to be sorted into several groups and locally sorts each group independently. In addition, an interleaving scheme is proposed to recover the performance degradation caused by the local sorting. A hardware architecture effective in reducin

To reduce the size of control ROM in microprogrammed processors, a new method for the minimisation of control ROM width is presented using integer linear programming (ILP), which guarantees optimal results and can solve problems of reasonable size with a small amount of computation time.