Kyungsik Choi
Yonsei University · Engineering
About the Lab
Professor Kyungsik Choi's research lab specializes in advanced integrated circuits and wireless communication systems, with a strong focus on millimeter-wave and terahertz (THz) technologies. The lab develops low-power, high-performance RF and mmWave front-ends, including transceivers, mixers, and beamforming architectures for high-data-rate applications such as 6G wireless systems and THz imaging. Key research directions include heterodyne receiver design, phase-locked loop alternatives, and innovative beamforming techniques for multi-input multi-output (MIMO) systems. The lab also explores biomedical applications of advanced imaging, such as preoperative nerve visualization using diffusion tensor tractography.
Research Overview
Research Output Trend
Figures are computed from collected data and may differ slightly.
Selected Papers
15OBJECTIVE: Facial nerve palsy is a common complication of treatment for vestibular schwannoma (VS), so preserving facial nerve function is important. The preoperative visualization of the course of facial nerve in relation to VS could help prevent injury to the nerve during the surgery. In this study, we evaluate the accuracy of diffusion tensor tractography (DTT) for preoperative identification of facial nerve. METHODS: We prospectively collected data from 11 patients with VS, who underwent pre
A wideband Internet of Things (IoT) transmitter (TX) employing open-loop binary frequency-shift keying (BFSK) modulator with a pseudo-randomized phase transition (PRPT) time and a single-supply Class-G harmonic rejection (HR) power amplifier (PA) is presented. The proposed open-loop phase switching modulator eliminates the data-rate limitation in a conventional phase-locked loop (PLL)-based closed-loop modulator, while the PRPT scheme increases the effective phase resolution with a better power
With growing interest in terahertz (THz) imaging, there has been an increasing demand for low-cost, low-power, and high-sensitivity THz receiver. Lately, heterodyne structures in CMOS technologies have been emerging as suitable solutions due to their advantages of low cost, high integration density, and high sensitivity. In order to take advantage of high sensitivity provided by heterodyne receivers, however, local-oscillator (LO) stabilization is essential, since the free-running oscillator wit
Phased-array systems are extensively utilized in wireless transmission and reception links operating at frequencies above 100 GHz to compensate for significant path loss. Regardless of beamforming architectures, the low-power implementation of a high-gain and low-noise receiver (RX) front-end (FE) plays a crucial role in large-scale RX arrays to maintain link margin. This article presents a 154 GHz low-power, high-gain, and low-noise CMOS RX FE adopting a proposed active mixer driven by a <inlin
A fully integrated 490-GHz heterodyne imager is reported. The imager adopts a second subharmonic resistive mixer wherein the transmission lines and small capacitors are used to enhance port-to-port isolation and the suppression of undesired local oscillator (LO) leakage and harmonic mixing components. The imager achieves a minimum noise equivalent power of 1.2 pW/Hz <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sup> while dissipating 26 mW fr
This work presents a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i>-band multi-input multi-output (MIMO) transmitter (TX) array with a four-element joint static/dynamic beamformer. The proposed beamformer combines a static beamformer and a space-time modulated dynamic array to produce a large number of concurrent beams with fewer array elements and multiple independent data streams, essentially achieving RF-domain beam number multiplicatio
A 915-MHz binary frequency-shift keying (BFSK) transmitter is proposed in this letter. The proposed transmitter architecture allows relaxing the frequency-tuning requirement of the conventional Internet of Things transceiver by the frequency-tripling signal-path topology. The tuning-range requirement is significantly improved down to 4% with the proposed signaling scheme, and this results in the ultralow-power synthesizer implementation. The proposed frequency tripler provides good spur rejectio
Recently, the increasing rates of facial nerve preservation after vestibular schwannoma (VS) surgery have been achieved. However, the management of a partially or completely damaged facial nerve remains an important issue. The authors report a patient who was had a good recovery after a facial nerve reconstruction using fibrin glue-coated collagen fleece for a totally transected facial nerve during VS surgery. And, we verifed the anatomical preservation and functional outcome of the facial nerve
A fully integrated 490-GHz receiver (RX) adopting a dual-locking receiver-based FLL (DL-RBFLL) is presented. The proposed RBFLL structure saves the power consumption by reusing the existing blocks in RX instead of the power-hungry blocks such as dividers and buffers operating at sub-THz. Contrary to the single-loop implementation, the dual-loop RBFLL, which consists of the coarse and fine locking loops, extends the locking range by six times with negligible additional power dissipation. In the R
A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency triple
A low-noise active leakage canceller (ALC) for radio frequency identification (RFID) transceiver is reported. The proposed ALC suppresses the strong transmitter (TX) leakage at the receiver (RX) input through continuous leakage tracking by employing an I/Q harmonic rejection switched-capacitor digital power amplifier (I/Q HR SC DPA). Compared to the analog feedback loop-based ALC, the proposed ALC minimizes the noise figure (NF) degradation in the RX and eliminates the large-size passive compone
This work presents a current-mode inverse Class-D digital PA (DPA) with enhanced power back-off (PBO) efficiency. The PA adopts extra switches, which allows the scaling in the output voltage swing by half, leading to (theoretically) 6 dB enhancement in PBO efficiency while maintaining (ideally) 100% drain efficiency (DE). Implemented in a 65 nm CMOS, the proposed DPA shows the improvement in DE by ×1.5 at 4.2 dB PBO in comparison with normalized Class-B PA while requiring only one transformer an
Research Areas
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