Minseok Kang

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL proces

13-kV 4H-SiC MOSFETs were successfully fabricated on a 125-μm-thick epitaxial layer on 6-in, N+ SiC substrates. Both lateral and longitudinal straggles from the P-well implant were investigated to optimize the JFET width and thus to avoid channel pinching in the JFET region. Channel lengths and channel mobilities were varied to investigate the effect of channel portions in determining the ON-state resistance of the 13-kV MOSFETs. It was discovered that the low channel mobility limits the transco

This article presents the short-circuit (SC) capability evaluation of TO-247-3 packaged silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) based on tests under different drain biases and gate biases. Compared with the 900-V Si super-junction MOSFET and the 1200-V Si trench-gate field-stop insulated gate bipolar transistor (IGBT), SiC devices show higher saturation current per die area, which requires more rigorous chip design consideration to reach an acceptable S

Stacking faults in the drift layer of 1.7 kV 4H-SiC MOSFETs result in body diode degradation, poor carrier conduction in on-state, and high leakage current in off-state. In this paper, the results of forward-bias stress on body diodes are analyzed in commercially available 1.7 kV 4H-SiC MOSFETs. Some devices show a significant degradation after forward-bias stress on the internal body diode. This implies that there are significant number of Basal Plane Dislocations (BPDs) present in these device

Metal, typically gold [Au], nanoparticles [NPs] embedded in a capping metal contact layer onto silicon carbide [SiC] are considered to have practical applications in changing the barrier height of the original contacts. Here, we demonstrate the use of silver [Ag] NPs to effectively lower the barrier height of the electrical contacts to 4H-SiC. It has been shown that the barrier height of the fabricated SiC diode structures (Ni with embedded Ag-NPs) has significantly reduced by 0.11 eV and 0.18 e

4H-SiC nano-channel field effect transistors (FETs) with various widths of 3 μm-50 nm have been fabricated by "top-down" approach using electron-beam lithography process. It has been demonstrated that the gate controllability of the SiC FETs is improved with decreasing channel width. In the fabricated devices the threshold voltage V(th) for the 50 nm-width nano-channel FETs shows a positive shift (ΔV(th) = 1.4 V) with respect to that of the reference FETs. The on-current degradation of the SiC n

In this study, nano-scale honeycomb-shaped structures with anti-reflection properties were successfully formed on SiC. The surface of 4H-SiC wafer after a conventional photolithography process was etched by inductively coupled plasma. We demonstrate that the reflection characteristic of the fabricated photodiodes has significantly reduced by 55% compared with the reference devices. As a result, the optical response Iillumination/Idark of the 4H-SiC photodiodes were enhanced up to 178%, which can

This work addresses the problem of minimizing power/ground noise with an important design parameter, which is the delay variations on the clock tree. Without considering the effect of delay variations on the polarity assignment, the resulting statistical clock skew may lead to a high probability of skew violation, which causes a low yield of design. Given distributions on the delay of each type of buffering elements and the interconnect delay from the clock source to every flip-flop with spatial

AIGaN/GaN nanowire (NW) FETs with a channel width down to -300 nm has been fabricated by "top-down" approach by using electron-beam lithography process. The fabricated AIGaN/GaN NW FETs showed the minimum threshold voltage -3 V, the gate leakage current -10(-10) A/mm, and the maximum transconductance -216 mS/mm, respectively. It has also been demonstrated that the gate controllability of the AIGaN/GaN FETs is improved with decreasing channel width. In the fabricated devices the threshold voltage

Utilizing a unique high NA optical system, a new methodology to measure device overlay accurately has been developed with a key differentiation. Historically, optical techniques to measure features below the image resolution require supporting measurement techniques to be used as a reference to anchor the optical measurement. This novel selfreference methodology enables accurate and robust optical metrology for device features after etch eliminating the need for external reference measurements s

Emerging device-based crossbar-array can improve energy efficiency and performance in Spiking Neural Network (SNN) that performs numerous addition and multiplication operations. However, for the large size of crossbar array, delay for SL voltage development increases due to large capacitances of bit-line, and area overhead of peripheral circuit increases significantly. In this paper, we propose STT-MRAM architecture for SNN by minimizing area overhead and operation delay with peripheral circuit

The clock distribution network in a synchronous digital circuit delivers a clock signal to every storage element, that is, clock sink in the circuit. However, since the continued technology scaling increases PVT (process-voltage-temperature) variation, the increase of clock-skew variation is highly likely to cause performance degradation or system failure at runtime. Recently, to mitigate the clock-skew variation, many researchers have taken a profound interest in the clock mesh network. However

In order to realize stable SiC (Silicon carbide) devices, metal contacts to SiC with suitable physical and electrical characteristics are required. For example, Ohmic contacts with low specific contact resistances and Schottky contacts with controlled barrier height (Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> ) between SiC and metal are among the most important factors for determining the performance of SiC devices. To date, extensive

온라인 게임 개발을 위해서는 서버 개발 기술이 중요하다. 왜냐하면 사용자들이 게임을 진행하는 클라이언트가 서버에 종속적으로 구현되기 때문이다. 본 연구는 서버 개발 기술 중 서버가 데이터를 데이터베이스에 저장하고 불러오는 데이터연동 방식을 연구하였다. 서버의 데이터 연동은 장소에 관계없이 게임을 이어서 진행할 수 있는 온라인게임의 특성 때문에 매우 중요한 사항이다. 본 논문에서는 여러 데이터연동 방식을 정의와 함께 제안하며 분류하였다. 제안된 방식들을 사례를 통해 평가하였다. 본 연구를 통해 향후 온라인 게임 서버의 개발 시에 게임의 특징에 맞는 데이터연동 방식을 선택할 수 있을 것으로 기대된다.