Myeong-Chul Kim
Korea Advanced Institute of Science and Technology · Computer Science
About the Lab
Professor Myeong-Chul Kim's research lab specializes in advanced electronic design automation (EDA), with a primary focus on global and detailed placement algorithms for integrated circuit design. The lab develops innovative, scalable, and timing- and routability-aware placement frameworks that integrate real-time congestion prediction, adaptive density modeling, and efficient optimization techniques. Key research directions include incremental timing-driven placement, routability-driven placement using lookahead routing, and primal-dual optimization for high-performance placement with minimal runtime overhead.
Research Overview
Research Output Trend
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Selected Papers
15We propose a self-contained, flat, quadratic global placer that is simpler than existing placers and easier to integrate into timing-closure flows. It maintains lower-bound and upper-bound placements that converge to a final solution. The upper-bound placement is produced by a novel look-ahead legalization algorithm. Our placer SimPL outperforms mPL6, FastPlace3, NTUPlace3, APlace2, and Capo simultaneously in runtime and solution quality, running 7.10 times faster than mPL6 (when using a single
We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global and detailed placement. In this framework, optimization is adaptive to current placement conditions through a new density metric. As a baseline, we leverage a recently developed at quadratic optimization that is comparable to prior multilevel frameworks in quality and runtime. A novel component called Progressive Local
At modern technology nodes, improving routability and reducing total wirelength are no longer sufficient to close timing. Incremental timing-driven placement (TDP) seeks to resolve timing violations while limiting the impact to the original placement in an effort to achieve timing closure. To improve the timing landscape in localized regions, some latches or nets may require specialized attention that may not be available in other traditional placement flows (e.g., wirelength-driven). To address
Highly-optimized placements may lead to irreparable routing congestion due to inadequate models of modern interconnect stacks and the impact of partial routing obstacles. Additional challenges in routability-driven placement include scalability to large netlists and limiting the complexity of software integration. Addressing these challenges, we develop lookahead routing to give the placer advance, firsthand knowledge of trouble spots, not distorted by crude congestion models. We also extend glo
Highly-optimized placements may lead to irreparable routing congestion due to inadequate models of modern interconnect stacks and the impact of partial routing obstacles. Additional challenges in routability-driven placement include scalability to large netlists and limiting the complexity of software integration. Addressing these challenges, we develop lookahead routing to give the placer advance, firsthand knowledge of trouble spots, not distorted by crude congestion models. We also extend glo
We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the original non-convex problem into\more convex"sub-problems. It generalizes the recent SimPL, SimPLR and Ripple algo- rithms and extends them. Empirically, ComPLx outper- forms all published placers in runtime and performance on ISPD 2005 and 2006 benchmarks.
We propose a self-contained, flat, force-directed algorithm for global placement that is simpler than existing placers and easier to integrate into timing-closure flows. It maintains lower-bound and upper-bound placements that converge to a final solution. The upper-bound placement is produced by a novel rough legalization algorithm. Our placer SimPL outperforms mPL6, NTUPlace3, FastPlace3, APlace2 and Capo simultaneously in runtime and solution quality, running 6.4 times faster than mPL6 and re
We propose a self-contained, flat, force-directed algorithm for global placement that is simpler than existing placers and easier to integrate into timing-closure flows. It maintains lower-bound and upper-bound placements that converge to a final solution. The upper-bound placement is produced by a novel rough legalization algorithm. Our placer SimPL outperforms mPL6, NTUPlace3, FastPlace3, APlace2 and Capo simultaneously in runtime and solution quality, running 6.4 times faster than mPL6 and re
The crucial parameters which determine the electrical and optical behavior of a heterojunction are the valence and conduction band offsets. We demonstrate that carefully performed in situ x-ray photoelectron spectroscopic measurements allow the evaluation of valence band offsets in strained heteroepitaxial systems on Si(001). The result obtained for a Si0.75Ge0.25 alloy layer agrees very well with the known value, indicating the reliability of the used method. For Si0.977C0.023 alloy layers tens
An important issue for the epitaxial growth of strained Si1−yCy alloy layers is the relation between substitutional and interstitial carbon incorporation, which is strongly influenced by the growth conditions. We use in vacuu x-ray photoelectron spectroscopy (XPS) to investigate Si1−yCy layers (y<2 at. %) grown pseudomorphically on Si(001) with constant carbon and Si fluxes, but at different growth temperatures. The total carbon concentration measured by secondary-ion mass spectroscopy (S
We report a transparent and flexible resistive random access memory (ReRAM) using a multi-thin-layer electrode. The transparent and flexible ReRAM includes a multi-thin-layer electrode that is transparent and flexible and an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layer as a transparent oxide material. When the multi-thin-layer
The existing methods of ransomware detection have limitations. To be specific, static analysis is not effective to obfuscated binaries, while dynamic analysis is usually restricted to a certain platform and often takes tens of minutes. In this paper, we propose a block-level monitoring system to detect potentially malicious cryptographic operations. We carry out statistical analysis to find heuristic rules to distinguish between normal and encrypted blocks. In order to apply the heuristic rule t
Research Areas
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