Sanggeun Jeon

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in th

This paper describes the general architecture and the signal-path behavior of a CMOS programmable phased-array receiver element that simultaneously operates at two frequencies between 6 and 18GHz (a tritave) while forming four independently controlled beams.

Power amplifiers (PAs) often exhibit instabilities giving rise to frequency divisions or spurious oscillations. The prediction of these instabilities requires a large-signal stability analysis of the circuit. In this paper, oscillations, hysteresis, and chaotic solutions, experimentally encountered in a high-efficiency class-E/F/sub odd/ PA with four transistors combined using a distributed active transformer, are studied through the use of stability and bifurcation analysis tools. The tools hav

A simple nonlinear technique for the design of high-efficiency and high-power switching-mode oscillators is presented. It combines existing quasi-nonlinear methods and the use of an auxiliary generator (AG) in harmonic balance. The AG enables the oscillator optimization to achieve high output power and dc-to-RF conversion efficiency without affecting the oscillation frequency. It also imposes a sufficient drive on the transistor to enable the switching-mode operation with high efficiency. Using

Power amplifiers (PAs) often exhibit instabilities leading to frequency division by two or oscillations at incommensurate frequencies. This undesired behavior can be detected through a large-signal stability analysis of the solution. However, other commonly observed phenomena are still difficult to predict and eliminate. In this paper, the anomalous behavior observed in a Class-E PA is analyzed in detail. It involves hysteresis in the power-transfer curve, oscillation, and noisy precursors. The

This paper presents a Ku-band monolithic multifunction transmitter and receiver chipset fabricated in 0.25-μm GaAs pseudomorphic high-electron mobility transistor technology. The chipset achieves a high level of integration, including a 4-bit 360° digital phase shifter, 5-bit 15.5-dB digital attenuator, amplifier and 9-bit digital serial-to-parallel converter for digital circuit control. Since the multifunction chipset includes a medium power amplifier and a low-noise amplifier, it features high

A class-E/F/sub odd/ high power amplifier (PA) using the distributed active transformer (DAT) is demonstrated at 29MHz. The DAT combines the output power from four VDMOS push-pull pairs. The zero voltage switching (ZVS) condition is investigated and modified for the class-E/F/sub odd/ amplifier with a non-ideal output transformer. All lumped elements including the DAT and the transistor package are modeled and optimized to achieve the ZVS condition and the high drain efficiency. The PA exhibits

A fully integrated medium power amplifier operating over the entire X-band is demonstrated in a 0.11-μm CMOS technology. A double-resonance technique is used for wideband input matching. At the output load, wideband class-E harmonic matching is performed for up to the third harmonic frequency to achieve high output power and efficiency. The amplifier exhibits measured small-signal gain exceeding 7.6 dB over a wide 3-dB bandwidth from 7.6 to 13.7 GHz. The output power and power added efficiency (

This paper presents a CMOS W-band amplifier adopting a novel neutralization technique for high gain and stability. The W-band amplifier consists of four common-source differential gain cells that are neutralized by a cross-coupled MOS–varactor pair. Contrary to conventional neutralizations, the proposed technique enables tunable neutralization, so that the gate-to-drain capacitance of transistors is accurately tracked and neutralized as the varactor voltage is adjusted. This makes the neutraliza

Abstract This article presents a D‐band CMOS envelope detector (ED) used for a wideband on‐off‐keying (OOK) receiver. The ED consists of an input balun and a differential common‐source pair. The input balun is designed in a low‐loss rat‐race coupler. The baseband output signal is taken at the common node of the differential pair while the carrier is simultaneously suppressed. The ED is fabricated in a low‐cost 65‐nm bulk CMOS technology. The measured average responsivity and noise equivalent pow

This chapter contains sections titled: Introduction Integrated Phased Arrays Fully Integrated mmWave Phased-array Transceiver Direct Antenna Modulation (DAM) Large-scale Integrated Phased Arrays Conclusions References

A design technique for kW level switching mode power amplifiers is presented. Several push pull pairs, independently tuned to Class E/Fodd, are combined by a distributed active transformer. The zero voltage switching (ZVS) condition is investigated and modified for the Class-E/Fodd amplifier with a non-ideal output transformer. All lumped elements including the DAT, the transistor package, and the input power distribution network are modeled and optimized to achieve the ZVS condition and the hig

This Letter presents a single‐pole single‐throw (SPST) switch for high‐power applications in the mm‐wave frequency band. A stacked‐FET structure is adopted in the shunt switching cell for reducing the insertion loss and improving the linearity of the switch. To enhance the isolation, the parasitic inductance of the stacked‐FET structure is resonated out by connecting a series capacitor. The number of stacked FETs in each shunt cell and the number of the shunt cells are optimised considering the

A uniplanar hybrid rat-race coupler has been fabricated on a flexible polyimide film for wearable and flexible RF applications. To enhance the reliability and repeatability of its operation in flexible environment, the coupler is designed using an asymmetric coplanar strip (ACPS) structure. Compared to the microstrip line or coplanar waveguide (CPW) structures, the ACPS requires no via holes through the substrate and reduces the number of air bridges. The dimension of the ACPS is determined by b

This paper presents a CMOS wideband amplifier operating in the full Ka-band, with a low gain variation. An inductive neutralization is applied to the amplifier to compensate for the gain roll-off in the high-frequency region. Neutralization inductance is carefully determined considering the tradeoff between stability and gain. To achieve a low gain variation over the full Ka-band, the amplifier employs the frequency staggering technique in which impedance matching for three gain stages is perfor