Woo Young Choi

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the <emphasis

A tunneling field-effect transistor (TFET) is considered one of the most promising alternatives to a metal–oxide–semiconductor field-effect transistor due to its immunity to short-channel effects. However, TFETs have suffered from low <emphasis emphasistype="smcaps" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</emphasis> -current, severe ambipolar behavior, and gradual transition between <emphasis emphasistype="smcaps" xmlns:mml="http://www.w3.org/

We have fabricated a 100-nm n-/p-channel I-MOS by adopting a novel structure. The proposed structure shows some advantages over the conventional one in terms of self-alignment and reduced number of photolithography masks. It leads to low fabrication cost, accelerated scaling down, and enhanced performance due to reduced parasitic elements. It shows a normal transistor operation with small subthreshold swing less than 11.8 mV/dec at room temperature. The n- and p-channel I-MOS have an ON/OFF curr

70-nm I-MOS devices have been integrated with 70-nm TFETs for the first time by adopting a novel process method. The integration of the I-MOS device with the TFET is meaningful in that it compensates for weak points of each device and implements both high-performance and low-power functionality on the same substrate. Additionally, by using SOI substrate and modifying mask layout, ON/OFF current ratio of the I-MOS device is increased dramatically by a factor of more than 1000 compared with our pr

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal–oxide–semiconductor field-effect transistors (MOSFETs) when supply voltage is redu

Abstract This study implements a highly uniform 3D vertically stack resistive random‐access memory (VRRAM) with a four‐layer contact hole structure. The fabrication process of a four‐layer VRRAM is demonstrated, and its physical and electrical properties are thoroughly examined. X‐ray photoelectron spectroscopy and transmission electron microscopy are employed to analyze the chemical distribution and physical structure of the VRRAM device. Multilevel capability, reliable endurance (&gt;10 4 cycl

A new electro-mechanical non-volatile memory (NVM) cell design is proposed and demonstrated for the first time. The fabricated cells operate with relatively low program/erase voltages and large sensing margin. Because only dielectric and metal layers are required, this cell design is suitable for post-CMOS fabrication. As the cell area is reduced, low operating voltages can be maintained by scaling the vertical dimensions of the cell. Nanometer-scale electro-mechanical memory technology is there

A novel biasing scheme for impact-ionization metal-oxide semiconductor (I-MOS) devices was proposed based on the physics of the device, which features negative biasing at the source region. To confirm the proposed idea, we have simulated an I-MOS whose gate length is 130 nm. According to the simulation results, by increasing the value of the reverse source-to-body bias, we can enhance the electrical characteristics of I-MOS devices. With the source bias of -6.5 V, a 130-nm I-MOS has a threshold

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The design and scalability of a nano-electro-mechanical memory (NEMory) cell are investigated via analytical modeling and finite element analysis (FEA) simulation. Proportionate scaling of all the cell dimensions provides for improved storage density together with low operating voltages and fast program/erase times. From FEA simulation, a 75-nm-long aluminum cantilever-beam NEMory cell is expected to

Hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) with dual-dielectric-constant (k) spacers have been fabricated and characterized. They have a heterogeneous gate dielectric layer which consists of high-k material (HfO2) and SiO2 at the source and drain side, respectively. The dual-k spacer has an inner high-k and outer SiO2 spacer. The fabricated dual-k-spacer HG TFETs show higher on/off current ratio, on-current and better subthreshold slope than control TFETs which use only

This paper suggests the practical implications of utilizing a high-density crossbar array with self-compliance (SC) at the conductive filament (CF) formation stage. By limiting the excessive growth of CF, SC functions enable the operation of a crossbar array without access transistors. An AlO x /TiO y, internal overshoot limitation structure, allows the SC to have resistive random-access memory. In addition, an overshoot-limited memristor crossbar array makes it possible to implement vector-matr

Complementary-metal-oxide-semiconductor(CMOS) and nanoelectromechanical (NEM) hybrid reconfigurable circuits are implemented for the first time using three-dimensional (3D) integration process. In addition, their operation is confirmed experimentally. For the fabrication of the 3D CMOS-NEM hybrid reconfigurable circuits, only the standard CMOS baseline process has been used except for the hydrofluoric acid vapor etch to release the NEM structures and focused-ion-beam patterning to define small p

Electrical characteristics of tunneling field-effect transistors (FETs) have been compared with those of metal–oxide–semiconductor FETs (MOSFETs) in terms of subthreshold swing (SS), on/off current ratio, off current and on current. According to simulation results, tunneling FETs have advantages over MOSFETs for low-power consumption: smaller SS below 60 mV/dec at room temperature, lower off current, higher on/off current ratio and better immunity to short channel effects. However, low on curren

The influence of intercell trapped charge (ITC)—the charge trapped at the inter-cell nitride regions by fringe electric fields during program and erase operations—on vertical NAND (VNAND) flash memory is investigated. In addition to conventional degradation mechanisms such as tunnel oxide damage, ITC deteriorates the transconductance and read current of VNAND flash memory cells. The influence of ITC-induced degradation on VNAND flash memory is discussed, using both simulation and experimental re