Cheol Seong Hwang 교수

A ferroelectric-resistive random access memory consisting of a conductive BiFeO3 epitaxial thin film with a unipolar diode current modulated by electric polarization orientation is reported. This device has a memory that lasts for months, a sufficiently high on current and on/off ratio to permit ordinary sense amplifiers to measure “1” or “0”, and is fully compatible with complementary metal-oxide semiconductor processing.

Issues in the circuitry, integration, and material properties of the two‐dimensional (2D) and three‐dimensional (3D) crossbar array (CBA)‐type resistance switching memories are described. Two important quantitative guidelines for the memory integration are provided with respect to the required numbers of signal wires and sneak current paths. The advantage of 3D CBAs over 2D CBAs (i.e., the decrease in effect memory cell size) can be exploited only under certain limited conditions due to the incr

(Ba,Sr)TiO3 (BST) thin films with thicknesses ranging from 15 to 50 nm are prepared by a rf magnetron sputtering on Pt/SiO2/Si substrates. The dielectric constants of BST thin films increase with increasing deposition temperature and thicknesses. The leakage current increases with increasing deposition temperature and this prevents the deposition temperature of the 20 nm thick BST thin film from being increased to a value more than 640 °C. The leakage current is also critically dependent upon th

The ever‐increasing demand for higher‐capacity digital memory shows no sign of declining. The conventional strategy for meeting such demand, i.e. shrinking of the memory cell size, will no longer be useful at some point in the future, owing to economic reasons and performance degradation. Nevertheless, performance of computing systems will keep improving for the next generation information technology. This indicates the necessity to consider a fundamentally disparate approach to enhance memory t

The evolution of ferroelectricity in undoped-HfO₂ thin films is systematically studied by controlling the deposition temperature during atomic layer deposition.

Electrical conduction mechanisms for Pt/(Ba0.5Sr0.5)TiO3 (BST)/Pt, IrO2/BST/IrO2, and Pt/BST/IrO2 capacitors were studied. The Pt/BST/Pt capacitor shows a Schottky emission behavior with interface potential barrier heights of about 1.5–1.6 eV. The barrier height is largely determined by the surface electron trap states of the BST. The IrO2/BST interface shows an ohmic contact nature due to the elimination of the surface trap states as the result of the formation of strong chemical bonds between

Vertically integrated NAND (V-NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176-layer-stacked V-NAND flash memory is available on the market. Nonetheless, increasing the layers invokes