권대웅 교수

Negative capacitance (NC) FETs with channel lengths from 30 nm to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\mu \text{m}$ </tex-math></inline-formula> , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to

We report on negative capacitance FETs (NCFETs) with a 1.8-nm-thick Zr-doped HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate oxide layer fabricated on an FDSOI wafer. Hysteresis-free operation is demonstrated. When compared to a baseline that uses HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate oxide with the same thickness, a subthreshold swing (SS) steeper by more tha

With the recently increasing prevalence of deep learning, both academia and industry exhibit substantial interest in neuromorphic computing, which mimics the functional and structural features of the human brain. To realize neuromorphic computing, an energy-efficient and reliable artificial synapse must be developed. In this study, the synaptic ferroelectric field-effect-transistor (FeFET) array is fabricated as a component of a neuromorphic convolutional neural network. Beyond the single transi

We report on capacitive neural network using charge-stored memory cells. Threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> )-adjusted memory cells are used as capacitors with different capacitances in the synapse array. The capacitor array detects output voltage difference induced by capacitive coupling from input voltages when outputting the data of weighted memory cells in a read operation. Thus, power consumption is si

We report Negative Capacitance nFETs with a ~ 1 nm effective oxide thickness (EOT) gate stack. Experimental measurements show a clear steepening of the slope of the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> characteristic in the weak inversion regime, indicating that a capacitance matching takes place there. This leads to non-lin

We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested - per-stage delay as small as 7.2 ps.

Hardware neuromorphic systems are crucial for the energy-efficient processing of massive amounts of data. Among various candidates, hafnium oxide ferroelectric tunnel junctions (FTJs) are highly promising for artificial synaptic devices. However, FTJs exhibit non-ideal characteristics that introduce variations in synaptic weights, presenting a considerable challenge in achieving high-performance neuromorphic systems. The primary objective of this study is to analyze the origin and impact of thes

In recent years, neuromorphic computing has been rapidly developed to overcome the limitations of von Neumann architecture. In this regard, the demand for high‐performance synaptic devices with high switching speeds, low power consumption, and multilevel conductance is increasing. Among the various synaptic devices, ferroelectric tunnel junctions (FTJs) are promising candidates. While previous studies have focused on improving reliability of FTJs to enhance the synaptic behavior, low‐frequency n

A ferroelectric thin‐film transistor (FeTFT)‐based synaptic device with an indium–gallium–zinc oxide (IGZO) channel and a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure is reported. The fabricated FeTFT exhibits a highly linear conductance response (| α | = 0.21) with a large dynamic range ( G max / G min ≈ 53.2), although identical program pulses are applied to the device. In addition, because the inner metal layer of the FeTFTs has an MFMIS structure, the electric field is

We investigate the variability of a ferroelectric FET (FEFET) in program operation using low-frequency noise (LFN) spectroscopy. Contrary to the previous report, LFN characteristics of FEFETs differ significantly depending on the program [low threshold voltage (Vth)] or erase state [high Vth)] [Shin et al., IEEE Electron Device Lett. 43, 13 (2022)]. Furthermore, the 1/f noise variation of the FEFETs is much larger in the program state than that in the erase state. It is revealed that the change

Ferroelectric (FE) materials are key to advancing electronic devices owing to their non-volatile properties, rapid state-switching abilities, and low-energy consumption. FE-based devices are used in logic circuits, memory-storage devices, sensors, and in-memory computing. However, the primary challenge in advancing the practical applications of FE-based memory is its reliability. To address this problem, a novel polarization pruning (PP) method is proposed. The PP is designed to eliminate weakly