KAIST · 공학
Dipjyoti Das 교수의 연구실은 고굴절율(고κ) 페로일렉트릭 물질, 특히 허프니우ム질옥사이드(기반 HZO)를 활용한 차세대 메모리 소자 기술 개발에 집중하고 있습니다. 주로 FEFET(페로일렉트릭 필드효과 트랜지스터)와 DRAM 기술에 응용 가능한 초박막 고성능 페로일렉트릭 캐패시터의 실현을 목표로 하며, 고압 후열처리(HPPMA) 및 전계열 전극 등 혁신적 공정 기법을 통해 EOT(등가산화막 두께)를 5Å 이하로 저감하고, 높은 잔류분극(Pr)을 확보하는 데 성공했습니다. 특히 Zr 농도가 높은 HZO(1:3) 조성에서의 페로일렉트릭 성질 향상은 기존 1:1 HZO와의 기술적 전환을 이끌어내고 있습니다.
표시된 성과는 수집된 데이터 기준으로 산출되며, 일부 차이가 있을 수 있습니다.
In this article, we report the fabrication of Zr-rich high-k ferroelectric hafnium zirconium oxide (HZO) capacitor with TiN as the top and bottom electrodes demonstrating an equivalent oxide thickness (EOT) of 5.7 Å and remanent polarization (Pr) of ~16 μC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . High-k-value and low EOT was achieved by utilizing multiphase region of HZO as well as high pressure post metallization annealing (HPPM
In this letter, we report excellent ferroelectricity with high remanent polarization (Pr) in Zr rich hafnium zirconium oxide (HZO) films using high pressure post metallization annealing (HPPMA). HZO films annealed using rapid thermal annealing (RTA) show highest ferroelectricity when the Hf:Zr ratio is 1:1 and exhibit antiferroelectric property for Zr rich films. However, under HPPMA, Zr rich films demonstrate enhanced ferroelectric property as compared to 1:1 HZO films and the best result was o
In this study, we have carried out an in-depth analysis on the role of high-pressure annealing (HPA) conditions on ferroelectricity as well as the interfacial property of Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) capa
A Ferroelectric Field-Effect Transistor (FEFET) is a promising candidate for next-generation memory devices because it offers numerous advantages, such as its high speed, low energy profile, and nondestructive readout process. FEFETs merge logic and memory functionality in a single device, allowing efficient data transfer and a high packing density, which could make them vital for use in future in-memory computing architectures. Although issues related to the integration of perovskite materials
Achieving low equivalent oxide thickness (EOT) with CMOS-compatible materials is of prime importance for further miniaturization of dynamic random access memory (DRAM) technology. Despite several efforts made in this regard, especially by using high dielectric constant ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> ) materials, utilization of novel electrodes to counter
In this letter, we demonstrate an effective way to enrich the performance of HfxZr1-x O2 (HZO) energy storage capacitors (ESCs) by inserting Al2O3 dielectric interlayer (DIL) in the middle of HZO in TiN/HZO/TiN structure. The impact of DIL (1 Å, 5 Å and 10 Å) is investigated in three different HZO compositions [1:1, 1:2 and 1:3]. Irrespective of HZO composition, insertion of DIL at critical thickness enhances the energy storage density (ESD) and efficiency of the ESCs. Grazing incident X-ray dif
We experimentally demonstrate, for the first time, that the insertion of an Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> layer in the middle of the ferroelectric (FE) Hf <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</inf> Zr <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmln
White organic/polymer light emitting diode (WOLED/WPLED) processed from solution has attracted significant research interest in recent years due to their low device production cost, device flexibility, easy fabrication over large area including roll to roll and ability to print in various designs and shapes providing enormous design possibilities. Although WOLEDs fabricated using solution process lack their thermally evaporated counterparts in terms of device efficiency, remarkable progress has
The effects of the electron injection barrier on the charge transport, brightness and the electroluminescence (EL) properties of polymer light emitting diodes (PLEDs) with poly(9-vinylcarbazole) (PVK) as an emissive layer have been studied. By using Al and LiF/Al as the cathode in single layer PLEDs and diverse electron transporting layers (ETLs) such as 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP), 4,7-diphenyl-1,10-phenanthroline (BPhen) and 2,2',2''-(1,3,5-benzinetriyl)-tris(1-phenyl-1
Fabrication of efficient blue and white polymer light-emitting diodes (PLEDs) using a well charge balanced, core modified polyfluorene derivative, poly[2,7-(9,9'-dioctylfluorene)-co-N-phenyl-1,8-naphthalimide (99:01)] (PFONPN01), is presented. The excellent film forming properties as observed from the morphological study and the enhanced electron transport properties due to the inclusion of the NPN unit in the PFO main chain resulted in improved device properties. Bright blue light was observed
In this paper, we investigate the ferroelectric properties of Al₂O₃/Hf<SUB>0.5</SUB>Zr<SUB>0.5</SUB>O₂ (HZO) dielectric/ferroelectric (DE/FE) bilayer stack for different DE layer thickness and annealing temperature. The DE/FE stack showed enhanced remanent polarization (Pr) as compared to the reference HZO capacitor for very thin DE layer due to the charge induced by the leakage current through the DE layer. On the contrary, for higher DE layer thickness, this charge injection is suppressed and
A major roadblock for the integration of ferroelectric-field-effect transistors (FEFETs) at advanced technology nodes for embedded memory applications is their high, logic-incompatible write voltages. Herein, we explore Ge as a channel material to reduce write voltage of FEFET and report the first demonstration of p-type Ge-FEFETs with record low write voltages of ±1.4 V with a memory window (MW) of 0.6 V at DC and write voltages of ±1.4 V, ±1.8 V and ±2.4 V for MW of 0.2 V, 0.5 V and 0.8 V for
We experimentally demonstrate a novel gate stack engineering technique by introducing a Tunnel Dielectric Layer (TDL) between two Ferroelectric (FE) layers, significantly increasing the Memory Window (MW) in FEFETs. An $\gt 2 \mathrm{X}$ improvement, from $2.9 \mathrm{~V}$ in the reference device (without TDL) to $7.5 \mathrm{~V}$ in the $8 / 3 / 8$ configuration with TDL, was achieved within NAND thickness limit of $20 \mathrm{~nm}$ and write voltage $\leq 15 \mathrm{~V}$. Impact of FE and TDL
We report a framework for designing a ferroelectric gate stack for vertical NAND with efficient multi-bit performance by evaluating various gate stacks, including those with a tunnel dielectric layer (TDL), a gate blocking layer (GBL), different post-metallization annealing (PMA) temperatures and nanolaminates. Using the Memory Window (MW) slope as the primary design metric, our study reveals that the ferroelectric gate stack with both TDL and GBL has the potential to deliver the best multi-bit
