Ibrahim Abdo 교수

This article introduces a four-element 300-GHz-band bi-directional phased-array transceiver (TRX). The TRX utilizes the same antenna, signal path, and local oscillator (LO) circuitry to operate either in transmitter (TX) mode or receiver (RX) mode. The TX mode adopts the outphasing technique to increase the average output power for higher order modulation schemes by utilizing the two mixers that are connected directly to the antenna in a mixer-last fashion. The two signal paths also enable the c

This paper presents a 300GHz CMOS transceiver, which achieves a data rate of 34Gb/s. A 300GHz CMOS push-push subharmonic mixer is proposed to realize a low conversion loss of around -16.5dB with low power consumption. The proposed transceiver also achieves wireless communication in ch.13-23 (1.76Gbaud), ch.39-43 (3.52Gbaud), ch.52-53 (7.04Gbaud) and ch.59 (10.56Gbaud) defined in IEEE802.15.3d. The transmitter and receiver consume 272mW and 135mW from a 1V supply, respectively.

This paper presents a CMOS bi-directional phased-array transceiver that covers the frequency range from 242 to 280GHz. The array consists of 4 elements with beamforming ability in the H-plane of the on-PCB Vivaldi antennas. The LO phase-generation scheme enables two different architectures for TX and RX modes. The TX mode utilizes an outphasing architecture while the Hartley architecture is adopted in the RX mode. The maximum achieved baud rates in the TX mode and the RX mode are 26Gbaud and 18G

This letter presents a 300-GHz-band four-element phased-array transmitter (TX) consisting of two types of chips, CMOS and InP HBT, to achieve a high equivalent isotropically radiated power (EIRP) and wide beam coverage. The CMOS chips include mixers and control circuits for the phased-array operation and the InP HBT chips include 300-GHz-band power amplifiers (PAs) and Antipodal Vivaldi ON-chip antennas. The two types of chips are connected in a flip-chip-on-chip fashion to reduce losses. A meth

This letter presents a 300GHz hybrid transceiver using CMOS and InP-HEMT, which achieves a maximum data rate of 56Gb/s. A 300GHz CMOS transceiver with a mixer-last transmitter mixer-first receiver is utilized to up- and down-convert the V-band IF signal to the 300GHz-band, while InP-HEMT is used for PA and LNA design. The transceiver also achieves wireless communication in ch.13-24 (1.76Gbaud), ch.39-44 (3.52Gbaud), ch.52-54 (7.04Gbaud) and ch.59 (10.56Gbaud) with lower than -16.7dB EVM. 64QAM m

This paper presents a frequency doubler that operates at W-band and D-band frequencies between 100GHz to 123GHz. An optimized buffering method is proposed to achieve saturated output power as high as 5.5dBm with over 60dBc rejection of the fundamental frequency at -8dBm input power. The overall circuit power consumption is 116mW. The doubler was designed and implemented using 65nm CMOS technology.

In this paper, a 300GHz dielectric lens antenna made of PTFE (Teflon)material is introduced. The antenna is designed to be used in combination with an on-chip antenna which is possible to realize regarding the very short wavelength of the electromagnetic wave at 300GHz frequency. Using this combination in wireless transceivers improves the total antenna gain, and hence, the communication distance. The proposed antenna was measured and compared to a 26dBi horn antenna. The measured gain when the

L-2L de-embedding method was proved accurate at millimeter-wave (mm-wave) frequencies around 60GHz. However, it was never quantitatively compared to a more complicated method at frequencies as high as 100GHz. In this paper, L-2L and TRL de-embedding methods are compared by applying both on test structures fabricated using CMOS 65nm process. More focus will be given to the W-band frequencies by comparing the measurement results of a W-band amplifier with simulation results that are based on both

This paper presents the simulation of a new modulation scheme for passive RFID systems. The proposed modulation scheme can be used to achieve minimum RFID tag chip size with low power consumption simultaneously. The modulation scheme is tested by a carrier of 900MHz and data rate of 20Kbps. The simulation results have shown that the proposed modulation scheme reserves the continuity of the carrier signal, such as FSK & PSK. Meanwhile, the proposed modulation scheme can be detected by a low power

A 300GHz CMOS-only wireless transceiver that achieves a maximum data rate of 34Gb/s while consuming a total power of 0.41W from a 1V supply is introduced. A subharmonic mixer with low conversion loss is proposed to compensate the absence of the RF amplifiers in TX and RX as a mixer-last-mixer-first topology is adopted. The TRX covers 19 IEEE802.15.3d channels (13-23, 39-43, 52-53, 59).

The wide available bandwidth at the 300GHzband makes it one of the expected target bands of the 6G wireless systems as extremely high data rates will be in demand in the next decade. In this presentation, a 300GHz-band bidirectional transceiver implemented using 65nm CMOS will be introduced. The talk also includes the discussion about phasedarray implementation using the introduced transceiver.

This paper presents a design for a ring-based Voltage Controlled Oscillator, VCO. The proposed design covers a wide frequency range (2.9-14.7) GHz with moderate KVCO variation. A control circuit was designed to reduce the impact of PVT variations. The wide range was covered by controlling the number of the voltage controlled resistors, VCRs, and the number of capacitors connected to the outputs of the delay cells. The VCO was implemented, extracted and simulated using 28nm CMOS technology. A sup

This paper describes the design and characterization of a low-noise amplifier (LNA) module that achieves more than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$20-\text{dB}$</tex> gain from 276 to 327 GHz. A modified ridge coupler structure is used to increase the reliability of the transition between the monolithic microwave integrated circuit (MMIC) and waveguide by suppressing potential high-order modes excitation, resulting in bandwidth exte

This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9dBm output power with a simple single-ended circuit architecture r