서울대학교 · Engineering
Jae Jeong Kim 교수의 연구실은 나노구조 실리카 나노입자 및 구리 전착 공정을 중심으로 한 고성능 전자재료의 설계와 응용을 연구하고 있습니다. 특히, 화학기계평탄화(CMP)에 적합한 균일한 주름진 실리카 나노입자 제조 기술과 반도체 집적회로에서의 구리 배선 공정 최적화를 위한 전착 기반 금속화 공정 기술을 개발하고 있습니다. 연구는 나노소재의 구조 제어와 표면 조작을 기반으로 하며, 반도체 소자 제조 공정의 핵심 기술 혁신을 목표로 합니다.
표시된 성과는 수집된 데이터 기준으로 산출되며, 일부 차이가 있을 수 있습니다.
A simple one-pot method is reported for the fabrication of uniform wrinkled silica nanoparticles (WSNs). Rapid cooling of reactants at the appropriate moment during synthesis allowed the separation of nucleation and growth stages, resulting in uniform particles. The factors affecting particle size and interwrinkle distance were also investigated. WSNs with particle sizes of 65-400 nm, interwrinkle distances of 10-33 nm, and surface areas up to 617 m<sup>2</sup> g<sup>-1</sup> were fabricated. Fu
As a superior substituent for the chemical-vapor deposition and physical-vapor deposition (PVD) Cu processes in an ultralarge-scale integrated interconnection, electrodeposition on two kinds of electroless-plated Cu seed layers was investigated. Co(II) and formaldehyde were used as reducing agents for each electroless plating. Two samples of electroless-plated seed layers had relatively higher resistivity due to rough and irregular grains and weakly developed (111) texture, which are peculiariti
We investigated the effects of under layer pretreatments on Cu electroless deposition to optimize the resistivity and morphology of the Cu. The pretreatments used in the Cu electroless plating process consisted of the removal of the titanium oxide layer on the barrier metal, TiN, and the deposition of Pd to activate the TiN diffusion barrier layer. Surface pretreatment using a 1%HF solution to remove the native Ti oxide formed on a TiN diffusion barrier layer showed a remarkable surface conditio
