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A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB program schemes is proposed. A BL voltage modulated ISPP scheme was used as parallel MSB programming in order to reduce cell-to-cell interference caused by the order in which t

The premature loss of a maxillary primary first molar, in cases with class I molar relationship, has limited influence on the space in permanent dentition.

Despite wide applications of polymer-drug conjugates, there are only a few polymer-siRNA conjugates like poly(ethylene glycol) conjugated siRNA. In this work, reducible hyaluronic acid (HA)-siRNA conjugate was successfully developed for target specific systemic delivery of siRNA to the liver. The conjugation of siRNA to HA made it possible to form a compact nanocomplex of siRNA with relatively nontoxic linear polyethyleneimine (LPEI). After characterization of HA-siRNA conjugate by size exclusio

In this work, we present a 3D 128Gb 2bit/cell vertical-NAND (V-NAND) Flash product. The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1xnm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution. Also, a negative counter-pulse scheme realizes a tightly programmed cell distribution. In order to reduce the effect of a large WL coupling, a glitch-canceling discharge scheme and a pre-offset

Recently, the demand for 3b/cell NAND flash has been increasing due to a strong market shift from 2b/cell to 3b/cell in NAND flash applications, such as USB disk drives, memory cards, MP3 players and digital still cameras that require cost-effective flash memory. To further expand the 3b/cell market, high write and read performances are essential [1]. Moreover, the device reliability requirements for these applications is a challenge due to continuing NAND scaling to sub-30nm pitches that increa

Although alveolar bone support was significantly higher in the noncleft control group, a successful level of alveolar bone support was achieved for the permanent canine on the cleft site after secondary bone graft. There was no difference in alveolar bone support achieved for the permanent canine whether the type of the cleft was unilateral or bilateral.

A scalable wordline shielding scheme using dummy cell in NAND flash memory is presented to eliminate abnormal disturb of edge memory cell which causes to degradation of NAND flash performance. The proposed NAND flash is also able to improve more NAND scaling compared to conventional NAND string beyond sub-40 nm technology node. By using a proposed program scheme which includes an optimized bias voltage and adjusted Vth of dummy cell, almost abnormal disturbance of edge memory cell is removed and

In this paper, we investigated the membrane fouling mechanism according to the coagulant dosage in algal rich water using a ceramic membrane. The algae that were used in this experiment were <i>Microcystis</i> sp. of cyanobacteria, and the fouling mechanism was analyzed through irrigation and filtration resistance through a constant flow operation. The experimental results showed that the filtration resistance decreased as the coagulant dosage increased, but the irreversibility at above optimum

Abstract To develop biocompatible antimicrobial agent, oyster shell wastes were thermally calcined at different temperatures ranging from 300 to 1000 °C. The chemical compositions and properties of oyster shells were characterized. As such, crystallographic analysis presented that oyster shells had a hexagonal crystalline shape, and calcination process reduced their crystalline size, volume (grain dimension), and bond length, which strongly affected antimicrobial efficacy. Results showed that th

A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is fabricated by 45 nm floating-gate CMOS and single-crystal Si layer stacking technologies. To support fully compatible device performance and characteristics with conventional planar device, shared bitline architecture including Si layer-dedicated decoder and Si layer-compensated control schemes are also developed. By using the architecture and

A NAND flash memory device for sub-40-nm-node technology and beyond utilizing an asymmetric source/drain (S/D) structure to suppress short-channel effects and improve the th distribution is presented in this paper. The asymmetric S/D structure consists of a diffused junction and inversion layer which is induced by the fringe field of the gate bias voltage during NAND operation. To reduce the area overhead caused by the select transistors, a 64-cell NAND string, which is twice the number of cells