Masanori Natsui 교수

Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of today's VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us t

A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabrica

The demand for energy-efficient, high-performance microcontroller units (MCUs) for the use in power-supply-critical Internet-of-Things (IoT) sensor-node applications has witnessed a substantial increase. In response, research concerning the development of several low-power-consuming MCUs has been actively pursued. The performance level of such MCUs, however, has not been sufficient, thereby rendering them non-feasible for the use in IoT sensor-node applications that process a large number of rec

The development of new functional memories using emerging nonvolatile devices has been widely investigated. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) has become new technology platform to overcome the issue in power consumption of logic for the application from IoT to AI; however, STT-MRAM has a tradeoff relationship between endurance, retention, and access time. This is because the MTJ device used in STT-MRAM is a two-terminal device, and excessive read current for h

We demonstrate an SOT-MRAM, a nonvolatile memory using spin-orbit-torque (SOT) devices that have a read-disturbance-free characteristic. The SOT-MRAM fabricated by a 55-nm CMOS process achieves 60-MHz write and 90-MHz read operations with 1.2-V supply voltage under a magnetic-field-free condition. The SOT-MRAM is also implemented in a dual-port configuration utilizing three-terminal structure of the device, which realizes a wide bandwidth applicable to high-speed applications.

Recently, the demand for low-power, high-performance microcontroller units (MCUs) for power-supply-critical sensor node applications has been increasing. In response to this demand, the use of nonvolatile memory elements for realizing MCUs for sensor node applications has been actively researched and developed. The latest nonvolatile MCUs (NV-MCUs) demonstrated 32b operation at 30MHz [1] and 8b operation at 100MHz [2]. However, this performance level is not suitable for sensor node applications

Abstract A nonvolatile logic gate based on magnetic tunnel junction-based nonvolatile logic-in-memory (NV-LIM) architecture is designed for the implementation of compact and low-power binary neural network (BNN) hardware. The use of NV-LIM architecture for designing BNN hardware makes it possible to reduce both computational and data transfer costs associated with inference functions of deep neural networks. Through an experimental evaluation of a basic component of BNN hardware designed with NV

This paper describes the design of a nonvolatile CPU based on RISC-V that is an open-source and highly flexible instruction set architecture. This CPU incorporates nonvolatile registers utilizing magnetic tunnel junction (MTJ) device, as well as custom instructions specific to the control of these nonvolatile registers and an accelerator module embedded into the CPU architecture. These techniques enable efficient execution of intermittent operations suitable for energy-limited internet-of-things

Abstract Nonvolatile flip-flop (NVFF) is an important component for implementing an energy-efficient logic large-scale integration (LSI) circuit that utilizes nonvolatile memory (NVM) function of magnetic tunnel junction (MTJ) devices. NVFF must be highly reliable in data store and restore operations for nonvolatile power gating. This study proposes an NVFF that can detect arbitrary errors occurring when storing data to the embedded NVM caused by the stochastic behavior of MTJ devices. The perfo

A magnetic-tunnel-junction (MTJ)-based video coding hardware with an MTJ-write-error-rate relaxation scheme as well as a nonvolatile storage capacity reduction technique is designed and fabricated in a 90 nm MOS and 75 nm perpendicular MTJ process. The proposed MTJ-oriented dynamic error masking scheme suppresses the effect of write operation errors on the operation result of LSI, which results in the increase in an acceptable MTJ write error rate up to 7.8 times with less than 6% area overhead,

Abstract This paper describes an impact of magnetic-tunnel-junction (MTJ)-device-based nonvolatile circuit techniques and its application to energy-efficient and compact binary-neural-network hardware design. Two specific properties of the MTJ-based nonvolatile-circuit style serve as key technologies to improve energy efficiency and ensure operational reliability. The former is a nonvolatile memory function that can reduce memory-access cost by holding intermediate data close to the logic circui

In realizing a nonvolatile microcontroller unit (MCU) for sensor nodes in Internet-of-Things (IoT) applications, it is important to solve the data-transfer bottleneck between the central processing unit (CPU) and the nonvolatile memory constituting the MCU. As one circuit-oriented approach to solving this problem, we propose a memory access minimization technique for magnetoresistive-random-access-memory (MRAM)-embedded nonvolatile MCUs. In addition to multiplexing and prefetching of memory acce

A novel graph-based evolutionary optimisation technique that can be used to synthesise heterogeneous circuits consisting of various different components is proposed. The key idea is to introduce ‘circuit graphs with coloured terminals’ for modelling heterogeneous architectures. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.

A new VLSI CAD environment considering stochastic behavior of MTJ devices is proposed for the evaluation of not only the performance but also the reliability of MTJ/MOS-hybrid logic LSI. The proposed simulator allows users to support the design of MTJ/MOS-hybrid LSI by RTL/gate-level hardware description, whose simulation considering stochastic switching behavior of MTJ device can be done by analog-mixed-signal simulation with de-facto standard EDA tools. Through the design of a nonvolatile logi