김성광 교수

Next-generation wireless communication such as sixth-generation (6G) and beyond is expected to require high-frequency, multifunctionality, and power-efficiency systems. A III-V compound semiconductor is a promising technology for high-frequency applications, and a Si complementary metal-oxide-semiconductor (CMOS) is the never-beaten technology for highly integrated digital circuits. To harness the advantages of these two technologies, monolithic integration of III-V and Si electronics is benefic

The coming of the big-data era brought a need for power-efficient computing that cannot be realized in the Von Neumann architecture. Neuromorphic computing which is motivated by the human brain can greatly reduce power consumption through matrix multiplication, and a device that mimics a human synapse plays an important role. However, many synaptic devices suffer from limited linearity and symmetry without using incremental step pulse programming (ISPP). In this work, we demonstrated a charge-tr

Although they have attracted enormous attention in recent years, software-based and two-dimensional hardware-based artificial neural networks (ANNs) may consume a great deal of power. Because there will be numerous data transmissions through a long interconnection for learning, power consumption in the interconnect will be an inevitable problem for low-power computing. Therefore, we suggest and report 3D stackable synaptic transistors for 3D ANNs, which would be the strongest candidate in future

In this work, we fabricated the In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors (MOSFETs) with a MOS interface of Y2O3/In0.53Ga0.47As and recessed gate structure. We investigated the interfacial properties of the gate stack and the junction characteristics of the fabricated MOSFETs. Low subthreshold slope (SS = 110 mV/dec), high on/off current ratio (Ion/Ioff = 106), and high effective mobility of 1600 cm2/V·s were achieved in the MOSFETs at a sheet charge density (Ns) = 1.2 ×

Abstract The authors demonstrate improved switching voltage, retention, and endurance properties in HfZrO x (HZO)‐based n/p‐ferroelectric field‐effect transistors (FeFETs) via oxygen scavenging. Oxygen scavenging using titanium (Ti) in the gate stack successfully reduce the thickness of interfacial oxide between HZO and Si and the oxygen vacancy at the bottom interface of the HZO film. The n/p‐FeFETs with scavenging exhibit an immediate read‐after‐write with stable retention property and improve

Defect less semiconductor-on-insulator (-OI) by a cost-effective and low-temperature process is strongly needed for monolithic 3-D integration. Toward this, in this paper, we present a cost-effective fabrication of the indium gallium arsenide-OI structure featuring the direct wafer bonding (DWB) and epitaxial lift-off (ELO) techniques as well as the reuse of the indium phosphide donor wafer. We systematically investigated the effects of the prepatterning of the III-V layer before DWB and surface

In this letter, we propose the photo-responsible synaptic devices by using stackable GaAs photodetectors (PDs) and Ge-on-insulator (Ge-OI) synaptic transistors for the future three-dimensional (3D) artificial vision sensors. The photo-responsible synapse showed good photo-responding synaptic behaviors depending on the incident light to GaAs PD, which changes the hole injection into the Ge-OI transistors, resulting in the change in potentiation/depression characteristics. The training simulation

HfO₂-based ferroelectric (FE) materials have emerged as a promising material for non-volatile memory applications because of remanent polarization, scalability of thickness below 10 nm, and compatibility with complementary metal-oxide-semiconductor technology. However, in the metal/FE/insulator/semiconductor, it is difficult to improve switching voltage (<i>V</i> _sw), endurance, and retention properties due to the interfacial layer (IL), which inevitably grows during the fa

Abstract The study demonstrates HfZrO x (HZO)‐based Si ferroelectric field‐effect transistors (FeFETs) with a low operating voltage (1.5 V) and immediate read‐after‐write operation (100 ns) via HZO thickness scaling, electron‐beam‐irradiation (EBI) treatment, and interfacial layer (IL) scavenging. With these three strategies, reduced operating voltage, immediate read‐after‐write capability, and improved endurance (&gt;10 8 cycles) and retention (extrapolated 10‐year) characteristics are achieved

In this work, we demonstrated 3D sequential complementary field-effect-transistor (CFET) by direct wafer bonding (DWB) technique and a low-temperature process for monolithic 3D(M3D) integration using a high-performance top Ge (110)/<110> channel on bottom Si CMOS. Here, the maximum thermal budget was up to 400°c during the fabrication of top Ge FET, allowing high-performance heterogenous Ge/Si CFET without damage to bottom Si FETs. Furthermore, we systematically investigated the mobility enhance

In this paper, we fabricated In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As-on insulator (OI) MOSFETs on Si substrates with different doping types to mimic ground plane doping using direct wafer bonding and epitaxial lift-off (ELO) techniques. We investigated the impact of doping types on the ground plane and the backgate bi

In this study, we report on the fabrication and characterization of 3-D sequential complementary field-effect-transistors (CFETs) using the direct wafer bonding (DWB) technology and a low-temperature process for monolithic 3-D (M3D) integration. The device features a high-performance top Ge (110)/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\langle 110\rangle $ </tex-math></inline-formula> channel on a bot

In this study, we demonstrated heterogeneous 3D monolithic CFETs (mCFETs) by utilizing Ge (110)/<110> gate-all-around (GAA) nanosheet p-FETs as the top-tier transistors and Si (100)/<110> tri-gate n-FETs as the bottom-tier transistors. By minimizing the mobility difference between electrons and holes through this transport combination of heterogeneous channels, we demonstrated its potential for the next-generation logic. Notably, we achieved a record-high hole mobility of 1200 cm<sup xmlns:mml="

In this work, we fabricated n-In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOSCAPs) with a metal-oxide-semiconductor (MOS) interface of Y2O3/In0.53Ga0.47As. We investigated interfacial properties of the gate stack through the H2 ambient annealing process in MOSCAPs. We obtained an extremely low interface trap density of Dit = 1.8 × 1011 cm−2 eV−1. We compared the H2 annealing effect in different gate electrode materials of Ni and Pt. We determined that the Pt electrode was effective in m

In this work, we first investigated the electrical and heat dissipation characteristics during the operation of top devices in a 3D sequential complementary field-effect transistors (CFETs) with Ge channel as top devices. The investigation was carried out with different inter-layer dielectric (ILD) thicknesses: 70 nm, 210 nm, and 1.4 μm. As the ILD thickness became thinner, we observed a higher body factor. This scaling of ILD thickness resulted in improved performance in the inverter gain and m