이윤명 교수

A 1.0 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> general-purpose sensor node platform with heterogeneous multi-layer structure is proposed. The sensor platform benefits from modularity by allowing the addition/removal of IC layers. A new low power I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> C interface is introduced for energy efficient inter-layer communication with compat

Wireless sensor nodes have many compelling applications such as smart buildings, medical implants, and surveillance systems. However, existing devices are bulky, measuring >;1cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> , and they are hampered by short lifetimes and fail to realize the “smart dust” vision of [1]. Smart dust requires a mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</s

Wireless sensor nodes (WSNs) are essential elements for today's structural health monitoring (SHM). As the design technology for WSNs evolves, there have been continuous efforts to address challenges for WSNs such as short lifetime, high power consumption, and bulky volume. Recent trends show energy harvesting becoming a popular solution for extending the lifetime of WSNs; even implementing energy-autonomous systems is an option. Smaller WSN form factors have been developed for volume-limited ap

The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly restricts low-voltage operation since it results in a low ON -to- OFF current ratio at low supply voltages. This paper investigates extremely low-power circuits based on new Si/SiGe heterojunction tunneling transistors (HETTs) that have a subthreshold swing of . Device characteristics, as determined through technology computer aided design tools, are used to develop a Verilog-A device model to simulate and

The nature of repetitive learning and oblivion of memory enables humans to effectively manage vast amounts of memory by prioritizing information for long-term storage. Inspired by the memorization process of the human brain, an artificial synaptic array is presented, which mimics the biological memorization process by replicating Ebbinghaus' forgetting curve. To construct the artificial synaptic array, signal-transmitting access transistors and artificial synaptic memory transistors are designed

Accurate measurement of synchronization cycle time is required for ultra-low power wireless sensor nodes with stringent power budgets. A multi-stage gate-leakage-based timer with boosted charging is proposed to address the high jitter of prior-art gate-leakage-based timers. The key approaches are faster load capacitor charging, wider voltage swing, and an improved gain sensing inverter. The proposed timer reduces RMS jitter by 8.1× and synchronization uncertainty by 4.1×, which allows hourly tra

Recent work in ultra-low-power sensor platforms has enabled a number of new applications in medical, infrastructure, and environmental monitoring. Due to their limited energy storage volume, these sensors operate with long idle times and ultra-low standby power ranging from 10s of nW down to 100s of pW. Since radio transmission is relatively expensive, even at the lowest reported power of 0.2mW, wireless communication between sensor nodes must be performed infrequently. Accurate measurement of t

Abstract The rapid advancement of AI‐enabled applications has resulted in an increasing need for energy‐efficient computing hardware. Logic‐in‐memory is a promising approach for processing the data stored in memory, wherein fast and efficient computations are possible owing to the parallel execution of reconfigurable logic operations. In this study, a dual‐logic‐in‐memory device, which can simultaneously perform two logic operations in four states, is demonstrated using van der Waals ferroelectr

A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8× longer retention time, 5× lower refresh power and 30% reduced area compared with the lowest power eDRAM previously reported. With an area-efficient single inverter sensing scheme designed for R/W speed compatibility with ultra-low power processors, 58% array efficiency is maintained for memories as small as 2kb and for as few as 32 bits per bitline.

Bell's Law predicts continual reductions in the size of computing systems. We investigate the status of the next paradigm shift that will usher in ubiquitous computing - sub-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> sensor nodes. However, this form factor remains beyond the capabilities of modern integrated circuit design techniques due to battery size. This paper describes new ultra-low power circuit techniques applied to digital p

Standby power can dominate the power budgets of battery-operated ultra-low power processors, and reducing standby power is the key challenge for further power reduction. State-of-the-art ultra low voltage sensors consume hundreds of nW in wake mode and 100 pW or less in standby mode. Therefore, applying known circuit techniques for further standby power reduction is very challenging. In this paper, we extend known standby power reduction techniques for use in ultra-low power processors. In parti

True random number generators (TRNGs), which create cryptographically secure random bitstreams, hold great promise in addressing security concerns regarding hardware, communication, and authentication in the Internet of Things (IoT) realm. Recently, TRNGs based on nanoscale materials have gained considerable attention for avoiding conventional and predictable hardware circuitry designs that can be vulnerable to machine learning (ML) attacks. In this article, a low-power and low-cost TRNG develop

Designing an ultra-low power sensor node requires careful consideration of the system-level energy budget. Depending on applications, various components can dominate total energy. In this paper, we review three different system energy budget scenarios where any of the microprocessor, memory, and timer of a sensor node can dominate the energy budget. The design space and corresponding trade-offs for these three components are explored to suggest guidelines for the design of ultra-low power sensor

Designing an ultra-low power sensor node requires careful consideration of the system-level energy budget. Depending on applications, various components can dominate total energy. In this paper, we review three different system energy budget scenarios where any of the microprocessor, memory, and timer of a sensor node can dominate the energy budget. The design space and corresponding trade-offs for these three components are explored to suggest guidelines for the design of ultra-low power sensor

In modern digital systems, sequential logic circuits store and process information over time, whereas combinational logic circuits process only the current inputs. Conventional sequential systems, however, are complex and energy-inefficient due to the separation of volatile and nonvolatile memory components. This study proposes a compact, nonvolatile, and reconfigurable van der Waals (vdW) ferroelectric field-effect transistor (FeFET)-based sequential logic-in-memory (S-LiM) unit that performs s