Min Sup Choi
성균관대학교 Materials Science · 재료과학
민수취 교수의 연구실은 2차원 물질 기반의 고성능 전자 및 광전자 소자 개발을 핵심으로 하며, 특히 2D 물질과 금속 간의 상호작용을 최적화하고, 접합 형성, 도핑, 패터닝 기술을 통해 초박막 소자의 성능을 극대화하는 데 주력하고 있습니다. vdW 갭 없는 접합, 선택적 원자층 에칭, 화학 도핑 기반의 고순도 전도성 제어 등 혁신적인 공정 기술을 개발하여, 미래형 나노소자 및 양자 장치의 실현 가능성을 높이고 있습니다. 특히, 2D 반도체 소자의 핵심 과제인 접촉 저항과 슈트키 장벽 문제를 해결하기 위한 새로운 접근법을 지속적으로 탐색하고 있습니다.
표시된 성과는 수집된 데이터 기준으로 산출되며, 일부 차이가 있을 수 있습니다.
This paper demonstrates a technique to form a lateral homogeneous 2D MoS2 p-n junction by partially stacking 2D h-BN as a mask to p-dope MoS2. The fabricated lateral MoS2 p-n junction with asymmetric electrodes of Pd and Cr/Au displayed a highly efficient photoresponse (maximum external quantum efficiency of ∼7000%, specific detectivity of ∼5 × 10(10) Jones, and light switching ratio of ∼10(3)) and ideal rectifying behavior. The enhanced photoresponse and generation of open-circuit voltage (VOC)
An unconventional phase-change memory (PCM) made of In<sub>2</sub> Se<sub>3</sub> , which utilizes reversible phase changes between a low-resistance crystalline β phase and a high-resistance crystalline γ phase is reported for the first time. Using a PCM with a layered crystalline film exfoliated from In<sub>2</sub> Se<sub>3</sub> crystals on a graphene bottom electrode, it is shown that SET/RESET programmed states form via the formation/annihilation of periodic van der Waals' (vdW) gaps (i.e.,
Graphene formed via chemical vapor deposition was exposed to various plasmas (Ar, O2, N2, and H2) in order to examine its effects on the bonding properties of graphene to metal. After exposing patterned graphene to Ar plasma, the subsequently deposited metal electrodes remained intact, enabling the successful fabrication of field effect transistor arrays. The effects of the enhanced adhesion between graphene and metals were more evident from the O2 plasma than the Ar, N2, and H2 plasmas, suggest
Recent studies have intensively examined 2D materials (2DMs) as promising materials for use in future quantum devices due to their atomic thinness. However, a major limitation occurs when 2DMs are in contact with metals: a van der Waals (vdW) gap is generated at the 2DM-metal interfaces, which induces metal-induced gap states that are responsible for an uncontrollable Schottky barrier (SB), Fermi-level pinning (FLP), and high contact resistance (R<sub>C</sub> ), thereby substantially lowering th
The development of a controllable, selective, and repeatable etch process is crucial for controlling the layer thickness and patterning of two-dimensional (2D) materials. However, the atomically thin dimensions and high structural similarity of different 2D materials make it difficult to adapt conventional thin-film etch processes. In this work, we propose a selective, damage-free atomic layer etch (ALE) that enables layer-by-layer removal of monolayer WSe<sub>2</sub> without altering the physic
Abstract Doping is a key technique for forming complementary metal‐oxide‐semiconductor (CMOS) that is a basic building block for current state‐of‐the‐art semiconductor devices. However, conventional doping methods such as ion implantation are unsuitable for 2D materials due to their ultra‐thinness to accommodate substitutionally doped atomic structures and vulnerability to high energy ion bombardment. Chemical doping methods have been widely used for 2D materials to induce a charge exchange tran
Achieving low contact resistance (R<sub>C</sub> ) is one of the major challenges in producing 2D FETs for future CMOS technology applications. In this work, the electrical characteristics for semimetal (Sb) and normal metal (Ti) contacted MoS<sub>2</sub> devices are systematically analyzed as a function of top and bottom gate-voltages (V<sub>TG</sub> and V<sub>BG</sub> ). The semimetal contacts not only significantly reduce R<sub>C</sub> but also induce a strong dependence of R<sub>C</sub> on V<
The surface oxidation of 2D transition metal dichalcogenides (TMDs) has recently gained tremendous technological and fundamental interest owing to the multi-functional properties that the surface oxidized layer opens up. In particular, when integrated into other 2D materials in the form of van der Waals heterostructures, oxidized TMDs enable designer properties, including novel electronic states, engineered light-matter interactions, and exceptional-point singularities, among many others. Here,
Polycrystalline silicon films are used throughout the semiconductor industry in the fabrication of both metaloxide-semiconductor (MOS) and bipolar products. For example, in MOS products, doped polysilicon is used for gate and interconnection materials. In bipolar products, polysilicon is used for device isolation, passive resistors, or active base elements. While these films are usually used with different ranges of doping, stress measurement of doped polysilicon is not well reported. Earlier re
The potential of 2D materials in future CMOS technology is hindered by the lack of high-performance p-type field effect transistors (p-FETs). While utilization of the top-gate (TG) structure with a p-doped spacer area offers a solution to this challenge, the design and device processing to form gate stacks pose serious challenges in realization of ideal p-FETs and PMOS inverters. This study presents a novel approach to address these challenges by fabricating lateral p<sup>+</sup>-p-p<sup>+</sup>
In two-dimensional (2D) nanomaterial electronics, vertical field-effect transistors (VFETs), where charges flow perpendicular to the channel materials, hold promise due to the ease of forming ultrashort channel lengths by utilizing the thinness of 2D materials. However, the poor performance of p-type VFET arises from the lack of a gate-field-penetrating electrode with suitable work functions, which is essential for VFET operation. This motivated us to replace graphene (work function of ∼4.5 eV)
Vertical field effect transistors (VFETs) based on two-dimensional materials offer exceptional potential for next-generation electronic devices due to their atomically thin channels and scalability. However, achieving high-performance p-type VFETs (p-VFETs) presents substantial challenges, as these devices often face limitations in hole transport efficiency, leakage current suppression, and attainment of high on/off current ratios. This study introduces an ultrashort channel length (less than 3.