[Paper Review] Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device

Dewei Wang, Pavan Kumar Chundi+7 more|arXiv (Cornell University)|Jun 22, 2020

Advanced Memory and Neural Computing14 references4 citations

TL;DR

This paper presents an event-driven spiking neural network (SNN) architecture that achieves sub-300-nW power consumption by leveraging spike-driven clock generation and combined clock- and power-gating techniques. The design enables always-on keyword spotting and similar AI workloads with high inference accuracy while minimizing dynamic and static power through activity-aware clocking and power management, making it ideal for ultra-low-power intelligent edge devices.

ABSTRACT

Always-on artificial intelligent (AI) functions such as keyword spotting (KWS) and visual wake-up tend to dominate total power consumption in ultra-low power devices. A key observation is that the signals to an always-on function are sparse in time, which a spiking neural network (SNN) classifier can leverage for power savings, because the switching activity and power consumption of SNNs tend to scale with spike rate. Toward this goal, we present a novel SNN classifier architecture for always-on functions, demonstrating sub-300nW power consumption at the competitive inference accuracy for a KWS and other always-on classification workloads.

Motivation & Objective

• To address the high power consumption of always-on AI functions like keyword spotting in ultra-low-power devices.
• To exploit the temporal sparsity of input signals in always-on workloads for energy efficiency.
• To develop a spiking neural network (SNN) classifier that maintains competitive inference accuracy while operating below 300 nW.
• To integrate spike-driven clock generation and dual clock- and power-gating to minimize dynamic and leakage power.
• To enable practical deployment of always-on AI in battery-operated and energy-constrained systems.

Proposed method

• The SNN employs spike-driven clock generation, where clock signals are activated only when input spikes occur, reducing idle switching activity.
• Clock-gating is applied selectively to inactive processing units, minimizing dynamic power during periods of inactivity.
• Power-gating is used to shut down entire functional blocks when not in use, significantly reducing leakage power.
• The architecture integrates event-driven operation with hierarchical clock and power control to scale power consumption with spike rate.
• The design is optimized for low-voltage operation and leverages asynchronous logic to further reduce power overhead.
• The system is fabricated in a standard CMOS process and validated for real-time inference on keyword spotting and similar tasks.

Experimental results

Research questions

• RQ1 Can spike-driven clock generation effectively reduce dynamic power in always-on SNNs without compromising performance?
• RQ2 How much power reduction can be achieved through combined clock- and power-gating in SNNs for sparse input signals?
• RQ3 What is the minimum achievable power consumption for an SNN while maintaining competitive inference accuracy on keyword spotting tasks?
• RQ4 How does the integration of event-driven operation with power management techniques affect area and latency overhead?
• RQ5 Can the proposed architecture enable practical deployment of always-on AI in ultra-low-power edge devices?

Key findings

• The proposed SNN achieves a total power consumption of less than 300 nW during inference, demonstrating sub-300-nW operation.
• The system maintains competitive inference accuracy comparable to conventional DNNs on keyword spotting tasks.
• Spike-driven clock generation reduces dynamic power by eliminating idle clock cycles during silent periods.
• Clock- and power-gating together suppress both dynamic and leakage power, contributing to the ultra-low power operation.
• The architecture enables always-on functionality with minimal energy overhead, suitable for battery-powered edge devices.
• The design achieves a power-area efficiency suitable for integration into compact, low-energy intelligent systems.