[Paper Review] High-threshold and low-overhead fault-tolerant quantum memory

Sergey Bravyi, Andrew W. Cross+4 more|arXiv (Cornell University)|Aug 15, 2023

Quantum Computing Algorithms and ArchitectureComputer Science65 references13 citations

TL;DR

This paper presents an end-to-end fault-tolerant quantum memory protocol using high-rate LDPC quasi-cyclic codes, achieving a circuit-based threshold near 0.8% and substantial encoding efficiency compared to the surface code.

ABSTRACT

Quantum error correction becomes a practical possibility only if the physical error rate is below a threshold value that depends on a particular quantum code, syndrome measurement circuit, and decoding algorithm. Here we present an end-to-end quantum error correction protocol that implements fault-tolerant memory based on a family of LDPC codes with a high encoding rate that achieves an error threshold of $0.8\%$ for the standard circuit-based noise model. This is on par with the surface code which has remained an uncontested leader in terms of its high error threshold for nearly 20 years. The full syndrome measurement cycle for a length-$n$ code in our family requires $n$ ancillary qubits and a depth-7 circuit composed of nearest-neighbor CNOT gates. The required qubit connectivity is a degree-6 graph that consists of two edge-disjoint planar subgraphs. As a concrete example, we show that 12 logical qubits can be preserved for nearly one million syndrome cycles using 288 physical qubits in total, assuming the physical error rate of $0.1\%$. We argue that achieving the same level of error suppression on 12 logical qubits with the surface code would require nearly 3000 physical qubits. Our findings bring demonstrations of a low-overhead fault-tolerant quantum memory within the reach of near-term quantum processors.

Motivation & Objective

• Motivate practical quantum error correction by reducing qubit overhead while maintaining a high fault-tolerance threshold.
• Identify LDPC code families with high encoding rate and distance suitable for near-term superconducting architectures.
• Develop a low-depth syndrome measurement circuit compatible with degree-6 Tanner graphs and thickness-2 connectivity.
• Demonstrate fault-tolerant memory capabilities including load-store and qubit readout operations.
• Provide a decoding framework capable of operating under circuit-based noise models for LDPC codes.

Proposed method

• Define quasi-cyclic LDPC codes QC(A,B) with length n=2ℓm and CSS-type check matrices H^X=[A|B], H^Z=[B^T|A^T].
• Prove that QC(A,B) codes have parameters [[n,k,d]] with k=2·dim(ker(A)∩ker(B)) and d determined by ker(H^X)∖rs(H^Z).
• Show Tanner graph G has thickness θ≤2, enabling a two-planar-layer realization suitable for hardware layouts.
• Describe a 7-layer depth syndrome measurement circuit that measures all checks using n ancillary qubits.
• Adapt Belief Propagation with an Ordered Statistics Decoder (BP-OSD) to the circuit-based noise model for decoding.
• Demonstrate fault-tolerant memory features including Pauli basis readout and inter-code logical measurements via extended Tanner graphs.

Experimental results

Research questions

• RQ1 Can high-rate LDPC quasi-cyclic codes provide fault-tolerant memory with a higher encoding rate than the surface code while maintaining a comparable threshold?
• RQ2 What are the practical connectivity and circuit-depth requirements to implement such codes on near-term superconducting hardware?
• RQ3 How effective is BP-OSD decoding under circuit-based noise for these LDPC codes?
• RQ4 To what extent can these codes preserve multiple logical qubits over long syndrome cycles with realistic physical error rates?
• RQ5 What are the comparative resource (qubits) efficiencies versus the surface code for equivalent logical qubit counts?

Key findings

• The quasi-cyclic LDPC codes achieve a pseudo-threshold close to 0.008, near the surface code threshold.
• A distance-12 code [[144,12,12]] with net rate 1/24 can outperform the distance-13 surface code for the same logical-qubit count in relevant error regimes.
• The 12-logical-qubit, 288-physical-qubit instance can preserve 12 logical qubits for ten million syndrome cycles at a physical error rate of 0.1%.
• Surface-code equivalents would require over 4000 physical qubits to reach similar suppression for 12 logical qubits in the stated regime, highlighting nearly 15× encoding overhead reduction.
• The full syndrome measurement cycle uses only 7 layers of CNOTs and a degree-6, thickness-2 Tanner graph, enabling feasible hardware implementations on superconducting architectures.
• BP-OSD decoding adapted to circuit-based noise demonstrates practical error suppression and supports code distance estimation within this framework.