Taewhan Kim

Carry-save-adder (CSA) is the most often used type of operation in implementing a fast computation of arithmetics of register-transfer-level design in industry. This paper establishes a relationship between the properties of arithmetic computations and several optimizing transformations using CSAs to derive consistently better qualities of results than those of manual implementations. In particular, we introduce two important concepts, operation duplication and operation split, which are the mai

In this paper, a new approach to the problem of allocating multiport memory modules for data storage is presented. Previous approaches divide the allocation problem into two separate steps: (i) grouping the variables (or registers) to form memory modules and (ii) determining the interconnections between the memory modules and functional units. Yet, there is no easy way to predict the result of step (ii) during step (i). In our approach, we place primary importance on the cost of interconnections

Carry-save-adder(CSA) is the most often used type of operation in implementing a fast computation of arithmetics of register-transfer level design in industry. This paper establishes a relationship between the properties of arithmetic computations and several optimizing transformations using CSAs to derive consistently better qualities of results than those of manual implementations. In particular, we introduce two important concepts, operation-duplication and operation-split, which are the main

We present an integrated approach to the solution of the scheduling, allocation (register and interconnections), and binding problems in high-level synthesis. Our algorithm synthesizes a data path from an unscheduled-data flow graph with an objective of minimizing both the number of control steps and total design area. Unlike most of the prior approaches in which interconnections are determined only in the final step of the synthesis process in our approach, scheduling of operations binding of o

The existing non‐hybrid image inpainting techniques can be broadly classified into two types. One is the texture‐based inpainting and the other is the structure‐based inpainting. One critical drawback of those techniques is that their inpainting results are not effective for the images with a mixture of texture and structure features in terms of visual quality or processing time. However, the conventional hybrid inpainting algorithms, which aim at inpainting images with texture and structure fea

In many embedded systems, particularly those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It has been known that there are high variations in memory-access delays depending on the ways of designing memory configurations and assigning arrays to memories. Furthermore, embedded-DRAM technology that provides efficient access modes is actively being developed, possibly becoming a mainstream in future embedded-system design. In th

We welcome you to the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, the premier technical forum for the embedded system research community. We have again joined CODES+ISSS and EMSOFT for Embedded Systems Week (ESWEEK), this time in beautiful Salzburg, Austria in early October. We hope that you will take the opportunity to enjoy this beautiful historic city while you are here. The Program Committee this year consisted of 29 experts from academic

Carry-save-adder (CSA) is one of the most widely used types of operation in implementing a fast computation of arithmetics. An inherent limitation of the conventional CSA applications is that the applications are confined to the sections of arithmetic circuit that can be directly translated into addition expressions. To overcome this limitation, from the analysis of the structures of arithmetic circuits found in industry, we derive a set of simple, but effective CSA transformation techniques oth

It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-time applications. The effectiveness comes from the fact that the amount of energy consumption is quadractically proportional to the voltage applied to the processor. The penalty is the execution delay, which is linearly and inversely proportional to the voltage. According to the granularity of units to which voltage scaling is applied, the DVS problem is divided in

Recent lightweight image captioning models using retrieved data mainly focus on text prompts. However, previous works only utilize the retrieved text as text prompts, and the visual information relies only on the CLIP visual embedding. Because of this issue, there is a limitation that the image descriptions inherent in the prompt are not sufficiently reflected in the visual embedding space. To tackle this issue, we propose ViPCap, a novel retrieval text-based visual prompt for lightweight image

In der Poetik des Aristoteles sind Peripetie und Wiedererkennung für die Beschreibung der Fabelstruktur von zentraler Bedeutung. Vor allem seine These, dass die Wiedererkennung am wirksamsten ist, wenn sie mit der Peripetie eintritt, ist in narratologischer Hinsicht hochinteressant, obwohl sie bisher oft missverstanden und nicht gebührend beachtet worden ist. Diese Arbeit geht den folgenden Fragen nach: Was wird eigentlich mit der Wiedererkennung, die mit der Peripetie eintritt, gemeint? Warum w

Histogram equalisation (HE), which redefines the distribution of grey‐levels in image, is an important step in image processing to enhance the image quality. Until now, numerous HE techniques have been proposed, among which major numbers have focused on solving the problem of how the grey‐levels in the histogram of an input image should be properly partitioned so that the image produced by collecting all equalisation results for the partitioned sub‐histograms leads to the quality enhancement of

Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studied in this thesis. Specifically, we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the problem of integrating the scheduling and allocation steps; and (4) the problem of data path synthesis for testability.